公开(公告)号：US12242202B2

公开(公告)日：2025-03-04

申请号：US17568151

申请日：2022-01-04

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Shih-Yuan Ma

IPC: G03F7/00

Abstract: The present disclosure provides a method for overlay error correction. The method includes: obtaining an overlay error based on a lower-layer pattern and an upper-layer pattern of a wafer, wherein the lower-layer pattern is obtained by first fabrication equipment through which the wafer passes, and the upper-layer pattern is obtained by exposure equipment; generating a corrected overlay error based on the overlay error and fabrication processes performed on the wafer after the first fabrication equipment and prior to the exposure equipment; and adjusting the exposure equipment based on the corrected overlay error.

公开(公告)号：US20250071985A1

公开(公告)日：2025-02-27

申请号：US18511029

申请日：2023-11-16

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： WEI-ZHONG LI

IPC: H10B20/25

Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate, a well region, a fuse medium, a gate electrode, a fuse doped region, a source/drain (S/D) region, and a resistance modification doped region. The well region is within the substrate with a first conductive type. The fuse medium is disposed over the substrate. The gate electrode is disposed over the fuse medium. The fuse doped region is under the gate electrode with a second conductive type different from first conductive type. The S/D region is adjacent to the fuse doped region with the second conductive type. The resistance modification doped region has the second conductive type and partially overlaps the fuse doped region.

公开(公告)号：US20250070014A1

公开(公告)日：2025-02-27

申请号：US18237015

申请日：2023-08-23

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： CHIN-LING HUANG

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: The present disclosure provides a semiconductor die structure including a substrate, a first supporting backbone, a first conductor block, and an air gap structure. The first supporting backbone is disposed on the substrate. The first conductor block is disposed on the first supporting backbone, and includes a first barrier layer and a first conductive layer disposed in the first barrier layer. The air gap structure is disposed on the substrate and in contact with the first supporting backbone and the first conductor block.

公开(公告)号：US20250069947A1

公开(公告)日：2025-02-27

申请号：US18945868

申请日：2024-11-13

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： WEI-CHEN PAN

IPC: H01L21/768 ,  C11D3/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: The present application discloses a semiconductor device with a composite barrier structure and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a first dielectric layer having a feature opening on a substrate; a composite barrier structure in the feature opening, wherein the composite barrier structure includes a barrier layer in the feature opening and an assisting blocking layer on the barrier layer; and a conductive feature on the assisting blocking layer; wherein the barrier layer includes tantalum, and the assisting blocking layer includes copper manganese alloy.

公开(公告)号：US12228608B2

公开(公告)日：2025-02-18

申请号：US18444745

申请日：2024-02-18

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Yi-Kai Chao

IPC: G01R31/28

Abstract: A probe station includes a frame, a platform, a testing equipment, a probe holder and at least one probe. The frame defines an accommodation space. The platform is connected with the frame. The platform has an opening. The opening is communicated with the accommodation space. The testing equipment is at least partially disposed in the accommodation space and is at least partially exposed through the opening. The probe holder is disposed on the platform. The probe is held by the probe holder. The probe holder is configured to control the probe to contact with a device under test disposed on the testing equipment through the opening.

公开(公告)号：US20250054864A1

公开(公告)日：2025-02-13

申请号：US18508603

申请日：2023-11-14

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： JEN-I LAI

IPC: H01L23/528 ,  H01L29/51

Abstract: An electrical structure and a method of manufacturing an electrical structure are provided. The electrical structure includes a substrate, a first insulation layer, a second insulation layer and an electrical contact. The first insulation layer and the second insulation layer are disposed over the substrate. The electrical contact extends through the first insulation layer and the second insulation layer. The electrical contact includes a first portion disposed in the first insulation layer and a second portion disposed in the second insulation layer. The first portion has a first width, and the second portion has a second width. A ratio of a difference between the first width and the second width to the first width is less than 10%.

公开(公告)号：US20250054859A1

公开(公告)日：2025-02-13

申请号：US18231453

申请日：2023-08-08

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Ying-Cheng CHUANG

IPC: H01L23/525 ,  H01L29/423

Abstract: A semiconductor device includes a substrate, a plurality of gate structures, and a fuse component. The substrate has an active region and a peripheral region surrounding the active region. The gate structures are disposed in the active region of the substrate. The fuse component is disposed at the peripheral region of the substrate. The fuse component has a poly silicon portion having a bottom tip pointing to the substrate, a dielectric film between the substrate and the poly silicon portion, and a conductive portion on the poly silicon portion. A method of forming a semiconductor device is also disclosed.

公开(公告)号：US12217815B2

公开(公告)日：2025-02-04

申请号：US18055847

申请日：2022-11-16

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chien Yu Chen

IPC: G11C29/46 ,  G11C29/12 ,  G11C29/36

Abstract: The present disclosure provides a memory testing system, including at least one memory device, a power supply, and a processor. The power supply is configured to provide a first reference voltage to the at least one memory device according to a control signal. The processor is configured to provide the control signal to control the power supply to vary the first reference voltage among multiple voltage levels and test the at least one memory device under the voltage levels to generate multiple first testing results corresponding to the voltage levels.

公开(公告)号：US12213306B2

公开(公告)日：2025-01-28

申请号：US17870073

申请日：2022-07-21

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Tse-Yao Huang

IPC: H01L27/108 ,  H10B12/00

Abstract: A semiconductor device includes a bottom barrier layer disposed over a semiconductor substrate, and a conductive contact disposed over the bottom barrier layer. The semiconductor device also includes a top barrier layer disposed over the conductive contact. The bottom barrier layer, the conductive contact, and the top barrier layer form an I-shaped structure. The semiconductor device further includes an isolation layer disposed adjacent to the I-shaped structure and extending into the semiconductor substrate. An air gap is surrounded by the isolation layer.

公开(公告)号：US12211905B2

公开(公告)日：2025-01-28

申请号：US17672138

申请日：2022-02-15

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Kuo-Hui Su

IPC: H01L29/40 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L29/423 ,  H01L29/51

Abstract: A method for preparing a recessed gate structure includes forming a recessed structure, wherein the recessed structure comprises a substrate with the recess extending into the substrate from a topmost surface of the substrate; forming a first functional layer to at least cover a sidewall of a recess of the recessed structure; forming a second functional layer to cover the first functional layer; performing a rapid thermal treatment to form an interfacial layer extending along an interface between the first functional layer and the second functional layer; and forming a conductive feature to fill up the recess.