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    Decryption semiconductor circuit
    74.
    发明授权
    Decryption semiconductor circuit 有权
    半导体电路用于解密

    公开(公告)号：EP1445889B1

    公开(公告)日：2007-04-11

    申请号：EP03250714.7

    申请日：2003-02-04

    Applicant: STMicroelectronics Limited

    Inventor： Dellow, Andrew

    IPC: H04L9/00 ,  H04N7/16 ,  H04N7/167

    CPC classification number: H04L9/0631 ,  H04L9/0827 ,  H04L2209/601

    Abstract: A semiconductor integrated circuit (39) comprising: a plurality of selectable pathways (23) inter-connected between a plurality of data sources and data destinations (11, 13, 15, 17, 19); a cryptographic circuit (9) connected to the selectable pathways (23) and arranged to selectively receive data at an input (24) from at least one of the data sources, to decrypt or encrypt the data in accordance with a key, and selectively provide the encrypted or decrypted data to at least one of the data destinations via an output (26); an instruction interpreter (29) arranged to receive as an input an instruction signal (33) and to generate therefrom an output (31) to control the plurality of selectable pathways (23) to select from which of the data sources the cryptographic circuit (9) receives data and to which destination the cryptographic circuit (9) provides data; the instruction interpreter (29) being configured such that the instruction signal (33) defines a data pathway configuration of the system, and such that it operates in accordance with a rule which limits the data pathway configurations which are selectable. Preferably, the instruction interpreter (29), cryptographic circuit (9) and data pathways (23) are all contained on a single monolithic semiconductor integrated circuit (39).

    Glitch-free multiplexer
    80.
    发明公开
    Glitch-free multiplexer 审中-公开
    Störimpulsfreier多路复用器

    公开(公告)号：EP1263139A3

    公开(公告)日：2006-07-05

    申请号：EP02253697.3

    申请日：2002-05-27

    Applicant: STMicroelectronics Limited

    Inventor： Dellow, Andrew ,  Elliot, Paul

    IPC: H03K17/00 ,  G06F1/08

    CPC classification number: G06F1/08 ,  H03K5/1252 ,  H03K17/005

    Abstract: A clock source selector for selecting either a first clock signal A or a second clock signal B in accordance with a switch request signal includes three retiming circuits each consisting of two clocked flip-flops. The switch request signal is first retimed (20,22) relative to clock A to give a signal P, is then retimed (24,26) relative to clock B to give a signal Q, and finally is retimed (28,30) relative to clock A to give a signal R. Selector circuitry (34,40,42) operates such that when signal Q is asserted, the second clock signal B is output, when neither signal P nor signal R, as combined by a NOR gate (34), are asserted, the first clock signal A is output, and at other times a zero level is output. The clock source selector can be used in an integrated circuit to form a glitch-free multiplexer.

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