公开(公告)号：KR1020130139107A

公开(公告)日：2013-12-20

申请号：KR1020120062862

申请日：2012-06-12

Applicant: 삼성전자주식회사

Inventor： 탁영조 ,  김재균 ,  김준연 ,  이재원 ,  최효지

IPC: H01L33/12 ,  H01L33/32 ,  H01L29/778

CPC classification number: H01L29/267 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/02458 ,  H01L21/02488 ,  H01L21/0254 ,  H01L29/16 ,  H01L29/2003 ,  H01L33/007 ,  H01L33/12

Abstract: Disclosed are a gallium nitride-based semiconductor capable of reducing a wafer's breakage and deformation with a decrease bow of the wafer and improving the uniformness of the outgoing wavelength and a method for manufacturing the same. The semiconductor device according to an embodiment of the present invention may include a silicon-based substrate doped with B and Ge simultaneously; a buffer layer on the silicon-based substrate; and a nitride laminated member on the buffer layer. Here, the doping concentration of B is higher than 10^19/cm^3 while the doping concentration of Ge can be higher than 10^19/cm^3.

Abstract translation: 公开了一种氮化镓系半导体及其制造方法，能够减少晶片的断裂和变形，并且提高出射波长的均匀性。 根据本发明实施例的半导体器件可以包括同时掺杂有B和Ge的硅基衬底; 硅基基板上的缓冲层; 和缓冲层上的氮化层叠体。 这里，B的掺杂浓度高于10 ^ 19 / cm ^ 3，Ge的掺杂浓度可高于10 ^ 19 / cm ^ 3。

公开(公告)号：KR1020120004159A

公开(公告)日：2012-01-12

申请号：KR1020100064872

申请日：2010-07-06

Applicant: 삼성전자주식회사

Inventor： 김준연 ,  채수희 ,  홍현기 ,  탁영조

IPC: H01L21/02 ,  H01L33/00 ,  H01L33/12 ,  H01S5/02

CPC classification number: H01L21/02658 ,  H01L21/0237 ,  H01L21/0242 ,  H01L21/02494 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/0265 ,  H01L33/0079 ,  H01L33/12 ,  H01S5/005 ,  H01S5/0207 ,  H01S5/32341

Abstract: PURPOSE: A substrate structure and a manufacturing method thereof are provided to reduce the failure factor generating in a manufacturing process by pattering a buffer layer to grow a semiconductor film to be separated into a chip unit. CONSTITUTION: A plurality of protrusions(112) is formed in one side of a substrate(110). A plurality of buffer layers(130) is formed on a plurality of protrusions. A semiconductor layer(150) is formed on the buffer layer. A plurality of buffer layers is patterned into the form including a plurality of holes(h). A plurality of holes is formed to form an undercut region(uc) between protrusions.

Abstract translation: 目的：提供一种衬底结构及其制造方法，以通过对缓冲层进行图案化以使半导体膜分离成芯片单元来减少在制造工艺中产生的故障因素。 构成：在基板（110）的一侧形成有多个突起（112）。 多个缓冲层（130）形成在多个突起上。 半导体层（150）形成在缓冲层上。 将多个缓冲层图案化成包括多个孔（h）的形式。 形成多个孔，以在突起之间形成底切区域（uc）。

公开(公告)号：KR101100431B1

公开(公告)日：2011-12-30

申请号：KR1020050111977

申请日：2005-11-22

Applicant: 삼성전자주식회사

Inventor： 김준연

IPC: H01S5/18

CPC classification number: H01S5/18305 ,  H01S3/109 ,  H01S5/0213 ,  H01S5/02484 ,  H01S5/041 ,  H01S5/141

Abstract: 본 발명은 2 개의 에탈론 필터를 이용하여 레이저광의 반치폭을 줄임으로써 2차 조화파 발생(Second Harmonic Generation; SHG) 결정의 효율을 증대시킨 고효율 외부 공진기형 면발광 레이저를 개시한다. 본 발명의 일 실시예에 따른 외부 공진기형 면발광 레이저는, 소정의 파장을 갖는 레이저광을 발생시키는 레이저칩; 상기 레이저칩 위에 형성된 제 1 에탈론 필터층; 상기 제 1 에탈론 필터층 위에 형성된 것으로, 상기 제 1 에탈론 필터층의 굴절률과 상이한 굴절률을 갖는 제 2 에탈론 필터층; 상기 레이저칩으로부터 이격되어 비스듬하게 배치된 제 1 미러; 상기 제 1 미러로부터 반사된 레이저광을 다시 상기 제 1 미러로 반사하며, 상기 레이저칩과 함께 공진기를 형성하는 제 2 미러; 및 상기 제 1 미러와 제 2 미러 사이의 광경로에 배치된 것으로, 상기 레이저칩에서 방출된 레이저광의 주파수를 2배로 변환하는 SHG 결정;을 포함하는 것을 특징으로 한다.

公开(公告)号：KR1020110123118A

公开(公告)日：2011-11-14

申请号：KR1020100042589

申请日：2010-05-06

Applicant: 삼성전자주식회사

Inventor： 정형수 ,  박영수 ,  채수희 ,  민복기 ,  김준연 ,  홍현기 ,  탁영조 ,  이재원

IPC: H01L27/15 ,  H01L33/38 ,  H01L33/42 ,  H01L33/00 ,  H01L33/32

CPC classification number: H01L33/0025 ,  H01L27/156 ,  H01L33/32 ,  H01L33/38 ,  H01L33/42

Abstract: PURPOSE: A vertical type light emitting device which includes a patterned light emitting part is provided to arrange an electrode on a region eliminated by patterning, thereby reducing light emitting loss due to the electrode. CONSTITUTION: A first electrode layer(120) is arranged on a substrate(110). A bonding metal layer(112) is arranged between the substrate and first electrode layer. A patterned third group nitride semiconductor layer(130) is arranged on the first electrode layer. A semiconductor layer comprises a semiconductor layer(131), an active layer(132), and a second semiconductor layer(133). A transparent electrode(150) is arranged as a flat shape on the semiconductor layer. A second electrode(160) is arranged on the transparent electrode.

Abstract translation: 目的：提供一种包括图案化发光部分的垂直型发光器件，用于通过图案化将电极排列在消除的区域上，从而减少由于电极引起的发光损失。 构成：第一电极层（120）布置在衬底（110）上。 在基板和第一电极层之间布置有接合金属层（112）。 图案化的第三组氮化物半导体层（130）布置在第一电极层上。 半导体层包括半导体层（131），有源层（132）和第二半导体层（133）。 透明电极（150）在半导体层上被设置为平坦的形状。 第二电极（160）布置在透明电极上。

公开(公告)号：KR1020110120019A

公开(公告)日：2011-11-03

申请号：KR1020100039499

申请日：2010-04-28

Applicant: 삼성전자주식회사

Inventor： 김준연 ,  탁영조 ,  이재원

IPC: H01L33/12 ,  H01L33/02

CPC classification number: H01L29/267 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0251 ,  H01L21/0254 ,  H01L33/12 ,  H01L33/02 ,  H01L33/145

Abstract: PURPOSE: A semiconductor device is provided to include a plurality of intermediate layers between neighboring clad layers, thereby reducing defect density and tensile stress. CONSTITUTION: A first buffer layer(12) and second buffer layer(14) are arranged on a substrate(10). A first n-type clad layer(16) is arranged on the second buffer layer. A first intermediate layer(18) is arranged on the n-type clad layer. A second intermediate layer(20) is arranged on the first intermediate layer. A second n-type clad layer(22) is arranged on the second intermediate layer.

Abstract translation: 目的：提供半导体器件以在相邻的覆盖层之间包括多个中间层，从而降低缺陷密度和拉伸应力。 构成：在衬底（10）上布置第一缓冲层（12）和第二缓冲层（14）。 第一n型覆盖层（16）布置在第二缓冲层上。 在n型覆盖层上设置第一中间层（18）。 第二中间层（20）布置在第一中间层上。 第二n型覆盖层（22）布置在第二中间层上。

公开(公告)号：KR1020110061911A

公开(公告)日：2011-06-10

申请号：KR1020090118453

申请日：2009-12-02

Applicant: 삼성전자주식회사

Inventor： 이재원 ,  채수희 ,  김준연 ,  탁영조

IPC: H01L33/38

CPC classification number: H01L33/382 ,  H01L2933/0016

Abstract: PURPOSE: A light emitting device and a manufacturing method thereof are provided to have an electrode structure which reduces a serial resistance and an operating voltage, thereby increasing light emitting efficiency. CONSTITUTION: An n-type clad layer(40) comprises a plurality of nitride semiconductor layers, a middle layer, and a via hole(65). The middle layer is arranged among nitride semiconductor layers. An active layer(50) is placed between the n-type clad layer and a p-type clad layer. A first electrode is placed in the via hole of the n-type clad layer. A second electrode is placed on one side of the p-type clad layer.

Abstract translation: 目的：提供发光器件及其制造方法以具有降低串联电阻和工作电压的电极结构，从而提高发光效率。 构成：n型覆盖层（40）包括多个氮化物半导体层，中间层和通孔（65）。 中间层布置在氮化物半导体层之间。 有源层（50）放置在n型覆层和p型覆层之间。 第一电极放置在n型覆盖层的通孔中。 第二电极放置在p型覆盖层的一侧。

公开(公告)号：KR100909966B1

公开(公告)日：2009-07-29

申请号：KR1020070053483

申请日：2007-05-31

Applicant: 삼성전자주식회사

Inventor： 강상구 ,  조창현 ,  강성모 ,  유상규 ,  김준연

IPC: G01R1/073

CPC classification number: G01R1/07314 ,  G01R31/2891 ,  Y10T29/49222

Abstract: A multi probe card unit, a probe test device including the multi probe card unit, and methods of fabricating and using the same are provided. The multi probe card unit may include at least one probe card including a first plurality of probes on a first surface of the at least one probe card and a second plurality of probes on a second surface of the at least one probe card.

Abstract translation: 提供了多探针卡单元，包括多探针卡单元的探针测试装置，以及制造和使用它的方法。 多探针卡单元可以包括至少一个探针卡，所述至少一个探针卡包括在所述至少一个探针卡的第一表面上的第一多个探针和在所述至少一个探针卡的第二表面上的第二多个探针。

公开(公告)号：KR1020090039061A

公开(公告)日：2009-04-22

申请号：KR1020070104473

申请日：2007-10-17

Applicant: 삼성전자주식회사

Inventor： 이상문 ,  강동훈 ,  전중석 ,  백광현 ,  김준연

IPC: H01L21/336 ,  B82Y40/00

Abstract: A transistor device and a manufacturing method thereof are provided to separate a substrate, a channel, a source, and a drain by forming an intermediate layer. A buffer layer(21a), an intermediate layer(22), and a semiconductor layer are successively formed on a top of a substrate(21). A mask layer is formed on a top of the semiconductor layer. A trench is formed till the buffer layer or the substrate. A substrate having the trench is oxidized through a dry oxidation or a wet oxidation. The trench is filled with insulation material. A device isolation film(23) is formed by filling the trench with an oxide film. The mask is removed by performing a chemical mechanical polishing process. The intermediate layer and the device isolation film are densified by performing an annealing process. A channel(25) is formed by performing a channel ion injection process. A gate insulation film(26) and a gate electrode layer(27) are formed on a top of the channel. A source(24a) and a drain(24b) are formed by performing a patterning process.

Abstract translation: 提供晶体管器件及其制造方法，通过形成中间层来分离衬底，沟道，源极和漏极。 缓冲层（21a），中间层（22）和半导体层依次形成在基板（21）的顶部上。 掩模层形成在半导体层的顶部上。 形成沟槽直到缓冲层或衬底。 具有沟槽的衬底通过干式氧化或湿式氧化而被氧化。 沟槽填充有绝缘材料。 通过用氧化膜填充沟槽来形成器件隔离膜（23）。 通过进行化学机械抛光工艺除去掩模。 通过进行退火处理使中间层和器件隔离膜致密化。 通过进行通道离子注入处理形成通道（25）。 栅极绝缘膜（26）和栅电极层（27）形成在通道的顶部。 通过进行图案化处理来形成源极（24a）和漏极（24b）。

公开(公告)号：KR1020080105644A

公开(公告)日：2008-12-04

申请号：KR1020070053483

申请日：2007-05-31

Applicant: 삼성전자주식회사

Inventor： 강상구 ,  조창현 ,  강성모 ,  유상규 ,  김준연

IPC: G01R1/073

CPC classification number: G01R1/07314 ,  G01R31/2891 ,  Y10T29/49222

Abstract: A multi probe card unit and probe test device is provided to increase inspection capacity of the EDS process conspicuously by testing a plurality of wafer at the same time. In a probe test apparatus, a probe(110) contacted with the chip pad of the formed on a wafer is included in a first probe card and a second probe card. The connection unit electrically connects a plurality of probe cards is included in. A multi-prop card unit(100) includes a connection unit electrically connecting a plurality of probe cards. The probe card is arranged in vertical or horizontal and the first and second card is arranged to be protruded opposite each other so that a plurality of wafers is accessed to the fist and second probe card.

Abstract translation: 提供多探针卡单元和探针测试装置，通过同时测试多个晶片来显着提高EDS工艺的检测能力。 在探针测试装置中，与形成在晶片上的芯片焊盘接触的探针（110）包括在第一探针卡和第二探针卡中。 连接单元电连接多个探针卡被包括在内。多路卡单元（100）包括电连接多个探针卡的连接单元。 探针卡被布置成垂直或水平，并且第一和第二卡片布置成彼此相对地突出，使得多个晶片被访问到第一和第二探针卡。

公开(公告)号：KR1020080068281A

公开(公告)日：2008-07-23

申请号：KR1020070005814

申请日：2007-01-18

Applicant: 삼성전자주식회사

Inventor： 김준연 ,  하경호 ,  조수행

IPC: H01L31/12 ,  H01L33/02

CPC classification number: H01S5/2232 ,  B82Y20/00 ,  H01S5/021 ,  H01S5/0218 ,  H01S5/0265 ,  H01S5/0425 ,  H01S5/12 ,  H01S5/124 ,  H01S5/2004 ,  H01S5/3434 ,  H01S5/4087

Abstract: A semiconductor optical device and a method for manufacturing the same are provided to reduce serial resistance by growing a semiconductor gain layer on a silicon substrate. A semiconductor optical device includes a silicon substrate(100) and a III-IV semiconductor gain layer(120). The III-IV semiconductor gain layer is provided on the silicon substrate. A division Bragg grating is formed in the silicon substrate or the III-IV semiconductor gain layer by a holography method or a lithography method. The III-IV semiconductor gain layer includes a gain medium having the constant as that of silicon. The gain medium has Ga(In)NAP or GaNAsP. The III-IV semiconductor gain layer is grown on the silicon substrate. The silicon substrate includes a first silicon layer(101), an insulation layer(102), and a second silicon layer(103).

Abstract translation: 提供半导体光学器件及其制造方法，以通过在硅衬底上生长半导体增益层来降低串联电阻。 半导体光学器件包括硅衬底（100）和III-IV半导体增益层（120）。 III-IV半导体增益层设置在硅衬底上。 通过全息方法或光刻方法在硅衬底或III-IV半导体增益层中形成分裂布拉格光栅。 III-IV半导体增益层包括具有与硅一样的常数的增益介质。 增益介质具有Ga（In）NAP或GaNAsP。 在硅衬底上生长III-IV半导体增益层。 硅衬底包括第一硅层（101），绝缘层（102）和第二硅层（103）。