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公开(公告)号：KR1019940003409B1
公开(公告)日：1994-04-21
申请号：KR1019910013279
申请日：1991-07-31
Applicant: 삼성전자주식회사
IPC: G11C11/407
CPC classification number: G11C11/4091 , G11C7/065
Abstract: The sense amplifier control circuit comprising a sense amplifier and a first sense amplifier driver, characterized in that a driver control circuit to keep current constant in the first sense amplifier driver, a bias circuit to keep current constant in the driving device and a means to drive the driver control circuit and the bias circuit are provided with the sense amplifier control circuit to reduce power noise.
Abstract translation: 读出放大器控制电路包括一个读出放大器和一个第一读出放大器驱动器，其特征在于驱动器控制电路在第一读出放大器驱动器中保持电流恒定，偏置电路在驱动装置中保持电流恒定，并且驱动装置 驱动器控制电路和偏置电路设置有读出放大器控制电路以降低功率噪声。
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公开(公告)号：KR1019940003397B1
公开(公告)日：1994-04-21
申请号：KR1019910006991
申请日：1991-04-30
Applicant: 삼성전자주식회사
IPC: G11C5/14
Abstract: The back bias generator includes normally a generator consisting of a driving part which drives a pump by input launch signal of an oscillator and a pum, an active generator consisting of an oscillator, a drive and a pump, detector which detects negative level of back bias voltage, a delay which delays output from the detector, a control and a power up circuit, to fasten level set up time of back bias voltage.
Abstract translation: 背偏置发生器通常包括由驱动部分组成的发电机，该驱动部分通过振荡器和泵的输入发射信号来驱动泵，由振荡器，驱动器和泵组成的有源发生器，检测负电平的反向偏置 电压，延迟来自检测器，控制和上电电路的延迟，以紧固反偏置电压的电平建立时间。
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公开(公告)号：KR1019930006621B1
公开(公告)日：1993-07-21
申请号：KR1019900012901
申请日：1990-08-18
Applicant: 삼성전자주식회사
Inventor： 황홍선
IPC: G11C11/407
Abstract: The circuit protects sense amplifiers from being applied with an excess voltage by comparing inputs with a reference voltage. The circuit comprises: a level change unit (30) to change a P-S/A driving signal which is generated by the row address access; a comparator (40) to compare a sensing enable line voltage (SAP) with a reference voltage (VREF), which is connected with the level change unit (30) and P-MOS transistor sensing unit (20); a trigger (50) for reverse triggering of the comparator output; and the trigger output voltage is linearly inverted by the bias unit (60).
Abstract translation: 电路通过将输入与参考电压进行比较来保护读出放大器免受过电压的影响。 电路包括：电平改变单元（30），用于改变由行地址访问产生的P-S / A驱动信号; 比较器（40），用于将感测使能线电压（SAP）与与电平变化单元（30）和P-MOS晶体管感测单元（20）连接的参考电压（VREF）进行比较; 用于反相触发比较器输出的触发器（50）; 并且所述触发输出电压被所述偏置单元（60）线性地反转。
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公开(公告)号：KR1019930003147A
公开(公告)日：1993-02-23
申请号：KR1019910013279
申请日：1991-07-31
Applicant: 삼성전자주식회사
IPC: G11C11/407
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Patent Agency Ranking
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公开(公告)号：KR101893895B1
公开(公告)日：2018-09-03
申请号：KR1020110136365
申请日：2011-12-16
Applicant: 삼성전자주식회사
IPC: G11C11/4096 , G11C7/10
CPC classification number: G06F12/00 , G06F13/16 , G06F13/1668 , G11C11/406
Abstract: 메모리시스템및 그동작제어방법이개시된다. 본발명에따른메모리시스템은, 복수의메모리셀과, 복수의메모리셀 중위크셀의정보를저장하는제1 저장부를포함하는메모리장치, 메모리셀의동작에관한동작명령신호를상기메모리장치로전송하며, 메모리장치로부터위크셀의정보를받아, 메모리장치의동작을제어하는메모리컨트롤러를포함하고, 메모리장치는, 동작명령신호가전송되면, 동작명령신호에대응하는메모리셀이상기위크셀인경우, 위크셀의정보를상기메모리컨트롤러로전송한다. 이에의해, 쓰기동작시위크메모리셀인경우에위크메모리셀에관한정보를메모리컨트롤러로제공하여동작시킴으로써, 정보의저장공간을최소화시키면서도, 위크메모리셀을노말메모리셀과독립적으로관리하여, 리프레쉬, 쓰기동작을효율적으로수행할수 있다.
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78.发明授权
公开(公告)号：KR101855295B1
公开(公告)日：2018-05-09
申请号：KR1020110091317
申请日：2011-09-08
Applicant: 삼성전자주식회사
CPC classification number: G11C5/145 , G11C7/12 , G11C11/1673
Abstract: 클램핑회로를갖는데이터리드회로, 이를포함하는불휘발성메모리장치및 불휘발성메모리장치의데이터리드방법이개시된다. 본발명의일 실시예에따른불휘발성메모리장치는, 메모리셀 및기준셀을포함하는셀 어레이와, 상기메모리셀과전기적으로연결되며, 데이터리드동작시데이터센싱라인에인가되는전압의레벨을클램핑하는클램핑회로및 상기기준셀에기인하는제1 전압에응답하여클램핑전압을생성하고, 상기클램핑전압을상기클램핑회로로피드백하는클램핑전압생성부를구비하는것을특징으로한다.
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公开(公告)号：KR101797565B1
公开(公告)日：2017-12-12
申请号：KR1020110083577
申请日：2011-08-22
Applicant: 삼성전자주식회사
CPC classification number: G11C29/24 , G11C29/00 , G11C29/76 , G11C29/785 , G11C2029/4402
Abstract: 본발명은불량페이지를관리하는메모리장치에대하여개시된다. 메모리장치는메모리셀 어레이와불량페이지맵을포함한다. 메모리셀 어레이는메모리셀들이배열되는제1 메모리블락과제2 메모리블락으로구성된다. 제1 메모리블락은메모리장치의최소한의보장메모리용량을제공하고, 제1 및제2 메모리블락은메모리장치의풀-메모리용량을제공한다. 시스템에서메모리장치의풀-메모리용량을사용할가능성이낮아짐에따라, 사용되지않을메모리셀들을갖는제2 메모리블락을제1 메모리블락의불량셀들의구제용으로사용할수 있다. 불량페이지맵은제1 메모리블락의페이지들각각의양, 불량여부를나타내는불량페이지위치정보를하나의비트로저장한다. 메모리장치는제1 메모리블락의불량페이지어드레스들을제2 메모리블락의최대페이지어드레스로부터역순으로대체한다. 메모리장치는메모리셀 어레이에서발생되는불량셀들을구제하는리던던시메모리셀 어레이를포함하지않을수 있다.
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公开(公告)号：KR1020140050239A
公开(公告)日：2014-04-29
申请号：KR1020120116356
申请日：2012-10-19
Applicant: 삼성전자주식회사
IPC: G11C11/408 , G11C11/406
CPC classification number: G11C11/40618 , G11C11/406 , G11C11/40611 , G11C11/408 , G11C29/023 , G11C29/028 , G11C2211/4065
Abstract: A refresh address generator includes a refresh address counting unit, a refresh address table, and an address selecting unit. The refresh address counting unit generates a counting signal by performing a counting operation in response to a refresh request signal, outputs at least one bit of the counting signal as an address selection signal, and outputs the remaining bits of the counting signal as a first refresh address. The refresh address table stores a row address of a memory cell having a data retention time shorter than a predetermined time, and outputs, as a second refresh address, the row address stored in a line corresponding to at least some bits of the first refresh address. The address selecting unit selectively outputs the first refresh address provided from the refresh address counting unit or the second refresh address provided from the refresh address table in response to the address selection signal.
Abstract translation: 刷新地址生成器包括刷新地址计数单元，刷新地址表和地址选择单元。 刷新地址计数单元通过响应于刷新请求信号执行计数操作产生计数信号，输出计数信号的至少一位作为地址选择信号，并输出计数信号的剩余位作为第一刷新 地址。 刷新地址表存储具有比预定时间短的数据保持时间的存储单元的行地址，并且将与存储在与第一刷新地址的至少一些位相对应的行中的行地址作为第二刷新地址输出 。 响应于地址选择信号，地址选择单元有选择地输出从刷新地址计数单元提供的第一刷新地址或从刷新地址表提供的第二刷新地址。
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