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公开(公告)号：KR1020150104712A
公开(公告)日：2015-09-16
申请号：KR1020140026377
申请日：2014-03-06
Applicant: 삼성전자주식회사
IPC: H01L21/203
CPC classification number: H01L21/76871 , C23C14/185 , C23C14/3464 , H01L21/2855 , H01L21/76802 , H01L21/76807 , H01L21/76831 , H01L21/76832 , H01L21/76843 , H01L21/76873 , H01L21/76879 , H01L23/481 , H01L2924/0002 , H01L2924/00
Abstract: 막 증착 시스템은 RF 스퍼터링 공정이 수행되는 제1 증착 챔버, DC 스퍼터링 공정이 수행되는 제2 증착 챔버, 제1 증착 챔버 및 제2 증착 챔버 사이에서 기판을 전달하는 이송 챔버, 제1 증착 챔버 내부에 배치된 제1 타겟에 RF 파워를 인가하는 RF 파워 공급부 및 제2 증착 챔버 내부에 배치된 제2 타겟에 DC 파워를 인가하는 DC 파워 공급부를 포함한다. RF 스퍼터링 공정 및 DC 스퍼터링 공정을 조합하여 균일한 프로파일의 도전막을 형성할 수 있다.
Abstract translation: 层沉积系统包括：用于执行RF溅射工艺的第一沉积室; 用于进行DC溅射工艺的第二沉积室; 输送室，其在第一和第二沉积室之间输送基板; 将RF功率施加到布置在第一淀积室中的第一靶的RF电源部; 以及将直流电力施加到布置在第二沉积室中的第二靶的直流电源部。 可以通过组合RF溅射工艺和DC溅射工艺来形成均匀轮廓的导电层。
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公开(公告)号：KR101354585B1
公开(公告)日：2014-01-22
申请号：KR1020070079098
申请日：2007-08-07
Applicant: 삼성전자주식회사
CPC classification number: H01L23/5256 , H01L2924/0002 , H01L2924/00
Abstract: 반도체 장치 및 그 형성 방법이 제공된다. 상기 반도체 장치는 기판 상에 위치하는 퓨즈 구조물을 포함한다. 층간 절연막이 상기 퓨즈 구조물을 덮는다. 제 1 콘택 플러그, 제 2 콘택 플러그 및 제 3 콘택 플러그가 상기 층간절연막을 관통하여 상기 퓨즈 구조물에 연결된다. 상기 제 1 콘택 플러그 및 상기 제 2 콘택 플러그와 각각 전기적으로 연결되는 제 1 도전 패턴 및 제 2 도전 패턴이 상기 층간절연막 상에 배치된다.
퓨즈, 더미 콘택 플러그, 전자 이동-
Patent Agency Ranking
公开(公告)号：KR1020090116478A
公开(公告)日：2009-11-11
申请号：KR1020080042452
申请日：2008-05-07
Applicant: 삼성전자주식회사
CPC classification number: H01L21/823807 , H01L21/823814 , H01L21/823835 , H01L29/665 , H01L29/7843
Abstract: PURPOSE: A fabrication method of a semiconductor device is provided to simplify a process and reduce time and costs by applying one of two silicide barriers to one dual stress liner. CONSTITUTION: In a fabrication method of a semiconductor device, a gate electrode(110) and source/drain regions(104,106) are formed on a first MOS area and a second MOS area opposite to the first MOS area. A silicide barrier is formed on the second MOS area while exposing the first MOS area. A first metal silicide(108) is formed on the gate electrode and a source/drain region of the first MOS area. A first stress(124) is formed on the first MOS area, and a second metal silicide is formed on a gate electrode and a source/drain region of an exposed second MOS area. A second stress liner(126) is formed on the second MOS area in which the second metal silicide is formed.
Abstract translation: 目的：提供半导体器件的制造方法，以通过将两个硅化物屏障中的一个施加到一个双重应力衬垫来简化工艺并减少时间和成本。 构成：在半导体器件的制造方法中，在与第一MOS区域相反的第一MOS区域和第二MOS区域上形成栅电极（110）和源极/漏极区域（104,106）。 在第二MOS区域上形成硅化物屏障，同时露出第一MOS区域。 第一金属硅化物（108）形成在栅极电极和第一MOS区域的源极/漏极区域上。 第一应力（124）形成在第一MOS区上，第二金属硅化物形成在暴露的第二MOS区的栅电极和源极/漏极区上。 在形成第二金属硅化物的第二MOS区上形成第二应力衬垫（126）。
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公开(公告)号：KR1020080020313A
公开(公告)日：2008-03-05
申请号：KR1020060083654
申请日：2006-08-31
Applicant: 삼성전자주식회사
IPC: H01L21/24 , H01L21/336
Abstract: A semiconductor device and a method for manufacturing the same are provided to enhance the reliability of a gate insulating layer by suppressing the increase of wire contact resistance. A semiconductor device includes a semiconductor substrate(200), a gate structure(215), source and drain regions(203), first and second spacers(213,220), and silicide layers(225a,225b). The gate structure is formed on the semiconductor substrate. The source and drain regions are formed at both sides of the gate structure on the substrate. The first spacer covers a lower side wall of the gate structure. The second spacer covers an upper side wall of the gate structure on the first spacer. The silicide layers are formed at an upper portion of the gate structure exposed by the second spacer.
Abstract translation: 提供半导体器件及其制造方法，通过抑制接线电阻的增加来提高栅极绝缘层的可靠性。 半导体器件包括半导体衬底（200），栅极结构（215），源极和漏极区（203），第一和第二间隔物（213,220）以及硅化物层（225a，225b）。 栅极结构形成在半导体衬底上。 源极和漏极区域形成在衬底上的栅极结构的两侧。 第一间隔件覆盖栅极结构的下侧壁。 第二间隔件覆盖第一间隔件上的栅极结构的上侧壁。 硅化物层形成在由第二间隔物暴露的栅极结构的上部。
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公开(公告)号：KR100809335B1
公开(公告)日：2008-03-05
申请号：KR1020060095113
申请日：2006-09-28
Applicant: 삼성전자주식회사
CPC classification number: H01L29/7843 , H01L21/31053 , H01L21/3185 , H01L21/823807 , H01L21/823412 , H01L27/088
Abstract: A semiconductor device and its manufacturing method are provided to prevent a lower structure from being attacked by practically controlling a thickness of a stress layer. A semiconductor substrate(100) includes a first transistor region, a second transistor region, and a boundary region. The first transistor region has a first gate electrode(125a) and a first source/drain region(121a). The second transistor region has a second gate electrode(125b) and a second source/drain region(121b). The boundary region is located on a boundary of the first and second transistor regions and has a third gate electrode(125c). A first stress layer(131) covers the first gate electrode of the first transistor region and the first source/drain region. The first stress layer is extended to the third gate electrode of the boundary region. A second stress region covers the second gate electrode of the second transistor region and the second source/drain region. The second stress layer is extended to the third gate electrode of the boundary region. Interlayer dielectrics(142,144) are formed on the second stress layer. The third gate electrode is covered with at least one of the first stress layer and the second stress layer. The top surface of the first stress layer or the second stress layer respectively located on upper surfaces of the first, second, and third gate electrodes has the same level on the basis of the semiconductor substrate.
Abstract translation: 提供一种半导体器件及其制造方法，以防止较低的结构被实际控制应力层的厚度所侵蚀。 半导体衬底（100）包括第一晶体管区域，第二晶体管区域和边界区域。 第一晶体管区域具有第一栅极电极（125a）和第一源极/漏极区域（121a）。 第二晶体管区域具有第二栅极电极（125b）和第二源极/漏极区域（121b）。 边界区域位于第一和第二晶体管区域的边界上，并且具有第三栅电极（125c）。 第一应力层（131）覆盖第一晶体管区域的第一栅极电极和第一源极/漏极区域。 第一应力层延伸到边界区域的第三栅电极。 第二应力区域覆盖第二晶体管区域的第二栅极电极和第二源极/漏极区域。 第二应力层延伸到边界区域的第三栅电极。 层间电介质（142,144）形成在第二应力层上。 第三栅电极被第一应力层和第二应力层中的至少一个覆盖。 分别位于第一，第二和第三栅电极的上表面上的第一应力层或第二应力层的顶表面在半导体衬底的基础上具有相同的水平。
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公开(公告)号：KR1020070107515A
公开(公告)日：2007-11-07
申请号：KR1020060040123
申请日：2006-05-03
Applicant: 삼성전자주식회사
IPC: H01L21/3065
CPC classification number: H01L21/68721
Abstract: A semiconductor plasma apparatus is provided to minimize pattern dispersion within a wafer and to maintain suitable productivity by applying a focus ring having a first and a second area made of materials having different conductivities. An electrostatic chuck(310) fixes a wafer by absorbing the wafer. A focus ring(330) is positioned to surround the edge portions of the electrostatic chuck. The focus ring consists of a first region(332) which is made of a first material and a second region(334) which is made of a second material which has a different conductivity from the first material.
Abstract translation: 提供半导体等离子体装置以使晶片内的图案分散最小化并且通过施加具有由具有不同导电性的材料制成的第一和第二区域的聚焦环来保持适当的生产率。 静电吸盘（310）通过吸收晶片来固定晶片。 聚焦环（330）被定位成围绕静电卡盘的边缘部分。 聚焦环包括由第一材料制成的第一区域（332）和由与第一材料具有不同导电性的第二材料制成的第二区域（334）。
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公开(公告)号：KR100761847B1
公开(公告)日：2007-09-28
申请号：KR1020060047120
申请日：2006-05-25
Applicant: 삼성전자주식회사
IPC: H01L21/304
Abstract: 본 발명은 베이스, 및 상기 베이스로부터 돌출되어 형성되고 연마 입자와 개구부를 갖는 연마층을 포함하는 연마 입자가 내재된 연마 패드(Fixed Abrasive Polishing Pad), 이의 제조 방법, 및 이를 포함하는 화학적 기계적 연마 장치를 제공한다.
연마 입자가 내재된 연마 패드, Fixed Abrasive Polishing Pad, 화학적 기계적 연마, Chemical Mechanical Polishing, 기공, 발포제Abstract translation: 提供了一种固定的研磨抛光垫，用于在抛光层的粘合表面上形成的开口和晶片的抛光层中包含浆料，其中包括在基底上具有开口的抛光层。 固定的抛光垫从包括具有抛光颗粒（36）和开口的抛光层（31）的基座（32）突出。 开口可以是孔（38）。 开口面积可以是抛光层面积的5〜30％。 可以选择二氧化铈颗粒，二氧化硅颗粒或氧化铝颗粒之一作为抛光颗粒。
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