公开(公告)号：KR1020110110583A

公开(公告)日：2011-10-07

申请号：KR1020100029982

申请日：2010-04-01

Applicant: 삼성전자주식회사

Inventor： 김상욱 ,  박재철 ,  김선일 ,  김창정

IPC: H01L31/115

CPC classification number: G01T1/242 ,  H01L31/085

Abstract: 이중 포토컨덕터를 구비한 엑스선 검출기가 개시된다. 개시된 이중 포토컨덕터를 구비한 엑스선 검출기는, 엑스선이 입사되는 제1 포토컨덕터층과, 제1 포토컨덕터층을 통과한 엑스선이 입사되는 제2 포토컨덕터층을 포함한다. 제1 포토컨덕터층과 제2 포토컨덕트층은 탠덤구조로 이루어져 있다. 제1 포토컨덕터층은 저 에너지 대역의 엑스선을 흡수하는 실리콘으로 이루어지며, 제2 포토컨덕터층은 실리콘 보다 높은 에너지 대역의 엑스선을 흡수하는 물질로 형성된다.

公开(公告)号：KR1020110051859A

公开(公告)日：2011-05-18

申请号：KR1020090108660

申请日：2009-11-11

Applicant: 삼성전자주식회사

Inventor： 김호정 ,  정우인 ,  신재광 ,  김선일 ,  송이헌 ,  김창정 ,  전상훈

IPC: H04N5/335

CPC classification number: H04N9/045 ,  H01L27/14643 ,  H04N5/3745

Abstract: PURPOSE: An image sensor and a method of operating the same are provided to reduce the generation of a noise and improving the resolution of the image sensor. CONSTITUTION: An image sensor comprises a pixel array including a plurality of pixel(100), a light detector(PS) for creating a detection current which is determined by the energy of light incident, a reset part(102) for creating a reference current by activated based on a reset signal which resets one or more pixels, and a conversion part(103) for creating a sensing voltage and a reference voltage by converting the sensed current into voltage.

Abstract translation: 目的：提供图像传感器及其操作方法以减少噪声的产生并提高图像传感器的分辨率。 构成：图像传感器包括：像素阵列，包括多个像素（100），用于产生由入射光的能量确定的检测电流的光检测器（PS）;用于产生参考电流的复位部分（102） 通过基于重置一个或多个像素的复位信号而被激活;以及转换部分（103），用于通过将感测的电流转换为电压来产生感测电压和参考电压。

公开(公告)号：KR1020100132308A

公开(公告)日：2010-12-17

申请号：KR1020090051060

申请日：2009-06-09

Applicant: 삼성전자주식회사

Inventor： 박재철 ,  김상욱 ,  이성훈 ,  김창정

IPC: H01L29/786 ,  G02F1/136

CPC classification number: H01L29/78603 ,  G02F1/136209 ,  H01L29/7869

Abstract: PURPOSE: A thin film transistor and a method for manufacturing the same are provided to reduce manufacturing cost by simultaneously implementing an active layer etching process and an optical barrier forming process using one mask. CONSTITUTION: An optical barrier(120) is formed on a substrate(110). An active layer(130) is formed on the optical barrier. Light is blocked to be radiated on an active layer using the optical barrier. A source electrode(160) and a drain electrode(170) are formed on the active layer. A gate insulating film(142) and a gate(150) are formed on the channel region(136) of the active layer.

Abstract translation: 目的：提供薄膜晶体管及其制造方法，以通过同时实施使用一个掩模的有源层蚀刻工艺和光学屏障形成工艺来降低制造成本。 构成：在衬底（110）上形成光学屏障（120）。 在光屏障上形成有源层（130）。 使用光学屏障将光阻挡在有源层上辐射。 源极电极（160）和漏电极（170）形成在有源层上。 栅极绝缘膜（142）和栅极（150）形成在有源层的沟道区（136）上。

公开(公告)号：KR1020100115220A

公开(公告)日：2010-10-27

申请号：KR1020090033845

申请日：2009-04-17

Applicant: 삼성전자주식회사

Inventor： 후아샹잉 ,  송이헌 ,  김창정 ,  김상욱 ,  김선일

IPC: H01L29/78

CPC classification number: H01L21/823807 ,  H01L27/0922 ,  H01L27/1225 ,  H01L27/1251 ,  H01L29/78645

Abstract: PURPOSE: An inverter, a method of manufacturing the same and a logic circuit comprising an inverter are provided to implement a logic circuit including an inverter by using an oxide semiconductor. CONSTITUTION: An inverter, a method of manufacturing the same and a logic circuit comprising inverter comprises. First and second transistors which are connected with each other. The channel of the first transistor includes a lower and upper layer. The channel of the second transistor is same as one of the upper and lower layer.

Abstract translation: 目的：提供一种逆变器及其制造方法以及包括逆变器的逻辑电路，以通过使用氧化物半导体来实现包括逆变器的逻辑电路。 构成：逆变器及其制造方法以及包括逆变器的逻辑电路。 第一和第二晶体管彼此连接。 第一晶体管的沟道包括下层和上层。 第二晶体管的沟道与上层和下层中的一个相同。

公开(公告)号：KR1020100063993A

公开(公告)日：2010-06-14

申请号：KR1020080122388

申请日：2008-12-04

Applicant: 삼성전자주식회사

Inventor： 박성호 ,  김창정 ,  송이헌 ,  김상욱 ,  박재철

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L21/8221 ,  H01L27/0688 ,  H01L29/66795 ,  H01L29/7869

Abstract: PURPOSE: A transistor and a manufacturing method thereof are provided to implement a stack transistor with a large on-current simultaneously using channel layers of the transistors. CONSTITUTION: At least one first transistor(T1) is formed on a substrate(SUB1). The first transistor includes a channel layer, a source, a drain, and a gate. The channel layer is comprised of an oxide semiconductor. The source and the drain are respectively contacted with both sides of the channel layer in a longitudinal direction. The gate covers both sides and the upper side of the channel layer in a width direction.

Abstract translation: 目的：提供晶体管及其制造方法，以同时使用晶体管的沟道层来实现具有大导通电流的堆叠晶体管。 构成：在衬底（SUB1）上形成至少一个第一晶体管（T1）。 第一晶体管包括沟道层，源极，漏极和栅极。 沟道层由氧化物半导体构成。 源极和漏极分别在纵向方向上与沟道层的两侧接触。 栅极在宽度方向上覆盖沟道层的两侧和上侧。

公开(公告)号：KR1020100037407A

公开(公告)日：2010-04-09

申请号：KR1020080096721

申请日：2008-10-01

Applicant: 삼성전자주식회사

Inventor： 김상욱 ,  송이헌 ,  김창정 ,  박재철 ,  김선일

IPC: H01L21/336

CPC classification number: H01L27/0883 ,  H01L27/1203

Abstract: PURPOSE: An inverter, a method for operating the same, and a logic circuit including the same are provided to obtain a transistor which can easily control a threshold voltage by forming a load transistor or a driving transistor with a double gate structure. CONSTITUTION: A driving transistor(T2) is connected to a load transistor(T1). Either the driving transistor or the load transistor has a double gate structure. The load transistor is a depletion mode transistor or a depletion mode transistor with a double gate structure. The driving transistor is an enhancement mode transistor or the enhancement mode transistor with a double gate structure. The channel layer of the load transistor and the driving transistor includes a ZnO-based oxide.

Abstract translation: 目的：提供一种反相器，其操作方法和包括该反相器的逻辑电路，以获得能够通过形成具有双栅结构的负载晶体管或驱动晶体管来容易地控制阈值电压的晶体管。 构成：驱动晶体管（T2）连接到负载晶体管（T1）。 驱动晶体管或负载晶体管都具有双栅极结构。 负载晶体管是耗尽型晶体管或具有双栅结构的耗尽型晶体管。 驱动晶体管是增强型晶体管或具有双栅极结构的增强型晶体管。 负载晶体管的沟道层和驱动晶体管包括ZnO基氧化物。

公开(公告)号：KR1020100022408A

公开(公告)日：2010-03-02

申请号：KR1020080081073

申请日：2008-08-19

Applicant: 삼성전자주식회사

Inventor： 김창정 ,  김상욱 ,  박진성

IPC: H01L21/20

CPC classification number: H01L29/7869

Abstract: PURPOSE: An oxide semiconductor and a thin film transistor comprising the same are provided to use an oxide semiconductor in a channel region by adding a new material to a Zn oxide. CONSTITUTION: An oxide semiconductor adds a lanthanum series substance to a Zn oxide series compound. The lanthanum series substance is selected from a group comprised of La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb and a compound. The compound contains at least two kind of elements. Zn oxide series compound is one of a Zn oxide, an In-Zn oxide or a Ga-In-Zn oxides. The oxide semiconductor is an amorphous oxide semiconductor.

Abstract translation: 目的：提供一种氧化物半导体和包含该氧化物半导体的薄膜晶体管，通过向Zn氧化物添加新材料，在沟道区域中使用氧化物半导体。 结构：氧化物半导体将镧系列物质添加到Zn氧化物系列化合物中。 镧系物质选自La，Ce，Pr，Nd，Pm，Sm，Eu，Gd，Tb，Dy，Ho，Er，Tm，Yb和化合物。 该化合物含有至少两种元素。 Zn氧化物系化合物是Zn氧化物，In-Zn氧化物或Ga-In-Zn氧化物中的一种。 氧化物半导体是非晶氧化物半导体。

公开(公告)号：KR1020100013717A

公开(公告)日：2010-02-10

申请号：KR1020080075349

申请日：2008-07-31

Applicant: 삼성전자주식회사

Inventor： 김창정 ,  김상욱 ,  김선일

IPC: H01L29/786 ,  H01L21/18

CPC classification number: H01L29/7869 ,  H01L29/26 ,  H01L29/06

Abstract: PURPOSE: An oxide semiconductor and a thin film transistor comprising the same are provided to reduce the change of a threshold voltage and improve mobility by adding a Hf for channel material into an oxide semiconductor. CONSTITUTION: In an oxide semiconductor, a channel(15) is installed to be corresponded to a gate(13). The channel includes an oxide semiconductor with added Hf into Ga-In-Zn oxide. A gate insulator(14) is formed between the gate and channel. Source and drains(16a,16b) are formed at the both side respectively touching with the channel. In the thin film transistor, the oxide is amorphous, or mixed crystalline, or a crystalline.

Abstract translation: 目的：提供一种氧化物半导体和包括该氧化物半导体的薄膜晶体管，以通过将氧化物半导体中的沟道材料添加Hf来减小阈值电压的变化并提高迁移率。 构成：在氧化物半导体中，通道（15）安装成对应于门（13）。 该沟道包括在Ga-In-Zn氧化物中添加了Hf的氧化物半导体。 栅极绝缘体（14）形成在栅极和沟道之间。 源极和漏极（16a，16b）形成在分别与沟道接触的两侧。 在薄膜晶体管中，氧化物是无定形的，或是混晶的，或是结晶的。

公开(公告)号：KR1020100008704A

公开(公告)日：2010-01-26

申请号：KR1020080069300

申请日：2008-07-16

Applicant: 삼성전자주식회사

Inventor： 김창정 ,  박영수

IPC: G06F3/041 ,  G06F1/00 ,  B82Y30/00

CPC classification number: G06F3/0436 ,  B82Y30/00 ,  G06F3/0416 ,  G06F2203/04108

Abstract: PURPOSE: A contactless touch panel using nanowire is provided to be manufactured to a large size and operated as contactless. CONSTITUTION: Multiple second transparent electrodes(120) meet at right angle in multiple nanowires in multiple first transparent electrodes. The multiple second transparent electrodes have strip shape. The second transparent substrate is arranged on the second transparent electrode. An ultrasonic generator(130) applies the pulse voltage to nanowires. It is bumped against into object approaching to nanowires and the ultrasonic echo sensor senses the ultrasonic wave coming back to nanowires.

Abstract translation: 目的：使用纳米线的非接触触摸面板被制造成大尺寸并作为非接触式操作。 构成：多个第二透明电极（120）在多个第一透明电极中的多个纳米线中以直角相交。 多个第二透明电极具有带状。 第二透明基板布置在第二透明电极上。 超声波发生器（130）将脉冲电压施加到纳米线。 碰撞到接近纳米线的物体中，超声回波传感器感测超声波回到纳米线。

公开(公告)号：KR1020090059494A

公开(公告)日：2009-06-11

申请号：KR1020070126376

申请日：2007-12-06

Applicant: 삼성전자주식회사

Inventor： 김창정 ,  이은하 ,  박영수 ,  박재철

IPC: H01L29/786

CPC classification number: H01L29/26 ,  H01L29/7869

Abstract: An oxide semiconductor and a thin film transistor including the same are provided to deposit a thin film with high resistance when controlling an oxygen pressure highly and to deposit the thin film with low resistance when controlling the oxygen pressure below a predetermined value. A gate(13) is formed on one region of a substrate(11). A gate insulation layer(14) is formed on the substrate and the gate. An oxide layer(12) is formed by thermal oxidation process on the Si surface of the substrate if the substrate is made of Si. A channel(15) is formed on the gate insulating layer corresponding to the gate. A source and a drain are formed in both sides of the channel and the gate insulating layer. The gate is formed by patterning the conductive material. The source and the drain are formed by using the conductive material.

Abstract translation: 提供氧化物半导体和包括该氧化物半导体的薄膜晶体管以在将氧气压力控制在预定值以下时，高度控制氧气压力时沉积具有高电阻的薄膜并将薄膜沉积成低电阻。 栅极（13）形成在基板（11）的一个区域上。 在衬底和栅极上形成栅极绝缘层（14）。 如果衬底由Si制成，则在衬底的Si表面上通过热氧化工艺形成氧化物层（12）。 在对应于栅极的栅极绝缘层上形成沟道（15）。 源极和漏极形成在沟道的两侧和栅极绝缘层中。 栅极通过图案化导电材料而形成。 源极和漏极通过使用导电材料形成。