Vector floating point test data class immediate instruction

    公开(公告)号:GB2525356A

    公开(公告)日:2015-10-21

    申请号:GB201514700

    申请日:2014-01-07

    Applicant: IBM

    Abstract: A Vector Floating Point Test Data Class Immediate instruction is provided that determines whether one or more elements of a vector specified in the instruction are of one or more selected classes and signs. If a vector element is of a selected class and sign, an element in an operand of the instruction corresponding to the vector element is set to a first defined value, and if the vector element is not of the selected class and sign, the operand element corresponding to the vector element is set to a second defined value.

    VECTOR FIND ELEMENT EQUAL INSTRUCTION

    公开(公告)号:SG11201404824TA

    公开(公告)日:2014-09-26

    申请号:SG11201404824T

    申请日:2013-03-07

    Applicant: IBM

    Abstract: Processing of character data is facilitated. A Find Element Equal instruction is provided that compares data of multiple vectors for equality and provides an indication of equality, if equality exists. An index associated with the equal element is stored in a target vector register. Further, the same instruction, the Find Element Equal instruction, also searches a selected vector for null elements, also referred to as zero elements. A result of the instruction is dependent on whether the null search is provided, or just the compare.

    CONVERT FROM ZONED FORMAT TO DECIMAL FLOATING POINT FORMAT

    公开(公告)号:SG11201402090WA

    公开(公告)日:2014-06-27

    申请号:SG11201402090W

    申请日:2012-11-13

    Applicant: IBM

    Abstract: Machine instructions, referred to herein as a long Convert from Zoned instruction (CDZT) and extended Convert from Zoned instruction (CXZT), are provided that read EBCDIC or ASCII data from memory, convert it to the appropriate decimal floating point format, and write it to a target floating point register or floating point register pair. Further, machine instructions, referred to herein as a long Convert to Zoned instruction (CZDT) and extended Convert to Zoned instruction (CZXT), are provided that convert a decimal floating point (DFP) operand in a source floating point register or floating point register pair to EBCDIC or ASCII data and store it to a target memory location.

    CONVERT TO ZONED FORMAT FROM DECIMAL FLOATING POINT FORMAT

    公开(公告)号:SG11201402088PA

    公开(公告)日:2014-06-27

    申请号:SG11201402088P

    申请日:2012-11-13

    Applicant: IBM

    Abstract: Machine instructions, referred to herein as a long Convert from Zoned instruction (CDZT) and extended Convert from Zoned instruction (CXZT), are provided that read EBCDIC or ASCII data from memory, convert it to the appropriate decimal floating point format, and write it to a target floating point register or floating point register pair. Further, machine instructions, referred to herein as a long Convert to Zoned instruction (CZDT) and extended Convert to Zoned instruction (CZXT), are provided that convert a decimal floating point (DFP) operand in a source floating point register or floating point register pair to EBCDIC or ASCII data and store it to a target memory location.

    Convert to zoned format from decimal floating point format

    公开(公告)号:AU2012360180A1

    公开(公告)日:2014-06-05

    申请号:AU2012360180

    申请日:2012-11-13

    Applicant: IBM

    Abstract: Machine instructions, referred to herein as a long Convert from Zoned instruction (CDZT) and extended Convert from Zoned instruction (CXZT), are provided that read EBCDIC or ASCII data from memory, convert it to the appropriate decimal floating point format, and write it to a target floating point register or floating point register pair. Further, machine instructions, referred to herein as a long Convert to Zoned instruction (CZDT) and extended Convert to Zoned instruction (CZXT), are provided that convert a decimal floating point (DFP) operand in a source floating point register or floating point register pair to EBCDIC or ASCII data and store it to a target memory location.

    80.
    发明专利
    未知

    公开(公告)号:DE68923262D1

    公开(公告)日:1995-08-03

    申请号:DE68923262

    申请日:1989-11-24

    Applicant: IBM

    Abstract: A multi-bit overlapped scanning multiplication system using overlapped partial products in a matrix, accepts and multiplies either sign-magnitude operands or signed binary operands without correction, conversion, or complementation of operands or results.

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