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公开(公告)号:GB2525356A
公开(公告)日:2015-10-21
申请号:GB201514700
申请日:2014-01-07
Applicant: IBM
Inventor: BRADBURY JONATHAN DAVID , SCHWARZ ERIC MARK
IPC: G06F9/30
Abstract: A Vector Floating Point Test Data Class Immediate instruction is provided that determines whether one or more elements of a vector specified in the instruction are of one or more selected classes and signs. If a vector element is of a selected class and sign, an element in an operand of the instruction corresponding to the vector element is set to a first defined value, and if the vector element is not of the selected class and sign, the operand element corresponding to the vector element is set to a second defined value.
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公开(公告)号:GB2524440A
公开(公告)日:2015-09-23
申请号:GB201513183
申请日:2013-12-11
Applicant: IBM
IPC: G06F9/30
Abstract: A Vector Generate Mask instruction. For each element in the first operand, a bit mask is generated. The mask includes bits set to a selected value starting at a position specified by a first field of the instruction and ending at a position specified by a second field of the instruction.
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公开(公告)号:CA2940915A1
公开(公告)日:2015-09-17
申请号:CA2940915
申请日:2015-03-11
Applicant: IBM
Inventor: SCHWARZ ERIC MARK , BUSABA FADI YUSUF , GSCHWIND MICHAEL KARL , SLEGEL TIMOTHY , SALAPURA VALENTINA , JACOBI CHRISTIAN , CAIN HAROLD WADE III
IPC: G06F9/46 , G06F12/0815
Abstract: Embodiments relate to implementing a coherence protocol. An aspect includes sending a request for data to a remote processor and receiving by a processor a response from the remote processor. The response has a transaction status of a remote transaction on the remote processor. The processor adds the transaction status of the remote transaction on the remote processor in a local transaction interference tracking table.
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公开(公告)号:MX2014010947A
公开(公告)日:2014-10-13
申请号:MX2014010947
申请日:2012-11-15
Applicant: IBM
Inventor: SLEGEL TIMOTHY , SCHWARZ ERIC MARK , BRADBURY JONATHAN DAVID , GSCHWIND MICHAEL KARL , JACOBI CHRISTIAN
IPC: G11C11/00
Abstract: Se provee una instrucción del conteo de carga a frontera de bloque que provee una distancia de una dirección de memoria especificada a una frontera de memoria especificada. La frontera de memoria es una frontera que no es cruzada en la carga de datos. La frontera puede ser especificada de una diversidad de maneras, incluyendo pero limitado a un valor variable en el texto de instrucción, un valor de texto de instrucción fijo codificado en el código de operación o una frontera a base de registro o puede ser determinada dinámicamente.
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公开(公告)号:SG11201404824TA
公开(公告)日:2014-09-26
申请号:SG11201404824T
申请日:2013-03-07
Applicant: IBM
Inventor: BRADBURY JONATHAN DAVID , SLEGEL TIMOTHY , SCHWARZ ERIC MARK , GSCHWIND MICHAEL KARL
Abstract: Processing of character data is facilitated. A Find Element Equal instruction is provided that compares data of multiple vectors for equality and provides an indication of equality, if equality exists. An index associated with the equal element is stored in a target vector register. Further, the same instruction, the Find Element Equal instruction, also searches a selected vector for null elements, also referred to as zero elements. A result of the instruction is dependent on whether the null search is provided, or just the compare.
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公开(公告)号:SG11201402090WA
公开(公告)日:2014-06-27
申请号:SG11201402090W
申请日:2012-11-13
Applicant: IBM
Inventor: CARLOUGH STEVEN , SCHWARZ ERIC MARK , SLEGEL TIMOTHY , GAINEY CHARLES JR , MITRAN MARCEL , COPELAND REID
IPC: G06F9/30
Abstract: Machine instructions, referred to herein as a long Convert from Zoned instruction (CDZT) and extended Convert from Zoned instruction (CXZT), are provided that read EBCDIC or ASCII data from memory, convert it to the appropriate decimal floating point format, and write it to a target floating point register or floating point register pair. Further, machine instructions, referred to herein as a long Convert to Zoned instruction (CZDT) and extended Convert to Zoned instruction (CZXT), are provided that convert a decimal floating point (DFP) operand in a source floating point register or floating point register pair to EBCDIC or ASCII data and store it to a target memory location.
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公开(公告)号:SG11201402088PA
公开(公告)日:2014-06-27
申请号:SG11201402088P
申请日:2012-11-13
Applicant: IBM
Inventor: CARLOUGH STEVEN , SCHWARZ ERIC MARK , SLEGEL TIMOTHY , GAINEY CHARLES JR , MITRAN MARCEL , COPELAND REID
IPC: G06F9/30
Abstract: Machine instructions, referred to herein as a long Convert from Zoned instruction (CDZT) and extended Convert from Zoned instruction (CXZT), are provided that read EBCDIC or ASCII data from memory, convert it to the appropriate decimal floating point format, and write it to a target floating point register or floating point register pair. Further, machine instructions, referred to herein as a long Convert to Zoned instruction (CZDT) and extended Convert to Zoned instruction (CZXT), are provided that convert a decimal floating point (DFP) operand in a source floating point register or floating point register pair to EBCDIC or ASCII data and store it to a target memory location.
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公开(公告)号:AU2012360180A1
公开(公告)日:2014-06-05
申请号:AU2012360180
申请日:2012-11-13
Applicant: IBM
Inventor: CARLOUGH STEVEN , SCHWARZ ERIC MARK , SLEGEL TIMOTHY , GAINEY JR CHARLES , MITRAN MARCEL , COPELAND REID
IPC: G06F9/30
Abstract: Machine instructions, referred to herein as a long Convert from Zoned instruction (CDZT) and extended Convert from Zoned instruction (CXZT), are provided that read EBCDIC or ASCII data from memory, convert it to the appropriate decimal floating point format, and write it to a target floating point register or floating point register pair. Further, machine instructions, referred to herein as a long Convert to Zoned instruction (CZDT) and extended Convert to Zoned instruction (CZXT), are provided that convert a decimal floating point (DFP) operand in a source floating point register or floating point register pair to EBCDIC or ASCII data and store it to a target memory location.
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公开(公告)号:GB2454816B
公开(公告)日:2012-02-22
申请号:GB0822115
申请日:2008-12-04
Applicant: IBM
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公开(公告)号:DE68923262D1
公开(公告)日:1995-08-03
申请号:DE68923262
申请日:1989-11-24
Applicant: IBM
Inventor: VASSILIADIS STAMATIS , SCHWARZ ERIC MARK , SUNG BAIK MOON
Abstract: A multi-bit overlapped scanning multiplication system using overlapped partial products in a matrix, accepts and multiplies either sign-magnitude operands or signed binary operands without correction, conversion, or complementation of operands or results.
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