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公开(公告)号:DE10040422C2
公开(公告)日:2002-09-19
申请号:DE10040422
申请日:2000-08-18
Applicant: INFINEON TECHNOLOGIES AG
Inventor: SAUERBREY JENS , WITTIG MARTIN , THEWES ROLAND
Abstract: A circuit arrangement in switched op.amp. technique has at least one switched op.amp and at least one sampling capacitor connected to the output of the op.amp. and a clock-pulse/signal generating device for generating at least two non-overlapping switched clock-pulses/signals (46,47).A device is provided for varying the switched clock phases (50,51) in which all switched clock pulses/signals are in the OFF-phase.
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公开(公告)号:DE10043440C2
公开(公告)日:2002-08-29
申请号:DE10043440
申请日:2000-09-04
Applicant: INFINEON TECHNOLOGIES AG
Inventor: WEBER WERNER , BERG HUGO VON DEN , THEWES ROLAND
Abstract: A magnetoresistive memory includes magnetoresistive memory cells disposed in a plurality of rows and/or columns. A bit line is connected to first poles of the memory cells of a column. A word line is connected to second poles of the memory cells of a row. A read voltage source is separately connectable to first ends of the word lines. A voltage evaluator has at least one input that is separately connectable to first ends of the bit lines via an evaluation line. A first terminating resistor branches from the evaluation line. An impedance converter has an input connected to the evaluation line and has an output separately connectable to second ends of the bit lines and word lines. The invention also relates to a method of reading magnetoresistive memories.
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公开(公告)号:DE59901952D1
公开(公告)日:2002-08-08
申请号:DE59901952
申请日:1999-09-17
Applicant: INFINEON TECHNOLOGIES AG
Inventor: WEBER WERNER , THEWES ROLAND
IPC: G11C11/14 , G11C11/15 , G11C11/16 , H01L21/8246 , H01L27/105 , H01L27/22 , H01L43/08
Abstract: The magnetoresistive memory has a reduced current density in the bit lines and/or word lines. This avoids electromigration problems. The current density is reduced such that a compact field concentration is attained, for example, by the use of ferrite in the area around the magnetic memory cells.
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公开(公告)号:DE10010946C2
公开(公告)日:2002-06-20
申请号:DE10010946
申请日:2000-03-06
Applicant: INFINEON TECHNOLOGIES AG
Inventor: THEWES ROLAND , LINNENBANK CARSTEN , KOLLMER UTE , SAUTER STEPHAN
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公开(公告)号:DE10034315A1
公开(公告)日:2002-01-31
申请号:DE10034315
申请日:2000-07-14
Applicant: INFINEON TECHNOLOGIES AG
Inventor: SAUERBREY JENS , KREUPL FRANZ , THEWES ROLAND , PAULUS CHRISTIAN
Abstract: The device has at least one first and one second electrode, whereby the second electrode is a flexible element extending freely in one direction that is flexible in the direction of the first electrode, and a measurement signal detector for detecting a variable distance between the first and second electrodes. The distance varies on the basis off an electric field acting on the two electrodes.
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公开(公告)号:DE59608209D1
公开(公告)日:2001-12-20
申请号:DE59608209
申请日:1996-06-03
Applicant: INFINEON TECHNOLOGIES AG
Inventor: THEWES ROLAND , PRANGE STEFAN , WOHLRAB ERDMUTE , WEBER WERNER
IPC: G01R19/165 , G06F7/501 , G06F7/52 , G06F7/523 , G06F7/53 , G06G7/12 , G06G7/16 , H03K5/08 , H03K17/30
Abstract: PCT No. PCT/DE96/00971 Sec. 371 Date Dec. 4, 1997 Sec. 102(e) Date Dec. 4, 1997 PCT Filed Jun. 3, 1996 PCT Pub. No. WO96/42049 PCT Pub. Date Dec. 27, 1996The circuit arrangement has two electrical quantities in the form of a first quadrature-axis current component (I1) and of a second quadrature-axis current component (I2) that are compared to one another. The circuit arrangement has a first inverter unit (n1, p1) and a second inverter unit (n2, p2). Respectively one output (50, 52) of the two inverter units ((n1, p1, (n2, p2)) are coupled to an input of the respectively other inverter unit (52, 53). A reset unit (5) that initiates the comparison of the currents when activated is located between the two outputs of the two inverter units (n1, p2). When the reset unit (5) is deactivated, the output datum obtained in the evaluation remains stable.
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公开(公告)号:DE10025580A1
公开(公告)日:2001-12-06
申请号:DE10025580
申请日:2000-05-24
Applicant: INFINEON TECHNOLOGIES AG
Inventor: THEWES ROLAND
IPC: G01N27/416 , G01N27/00 , G01N27/04 , G01N27/22 , G01N27/26
Abstract: Measurement using electronic chemo- and bio-sensors comprising a calibration substance is applied to the sensor, measuring the resulting electrical value, determinign the difference between measured and expected values to calculating a correction value and using this for compensation, during measurement of analytes, is new. A calibration substance is applied to the sensor, measuring the resulting electrical value. The difference between measured and expected values is determined, to calculate a correction value. This is used for compensation, during measurement of analytes. An Independent claim is included for corresponding apparatus. This includes a calibration system to determine and/or compensate difference in an electrical value. A controller (23) is provided for control and read-out of the sensor. A process controller carries out measurements with it. Preferred Features: The difference and/or correction value is stored in memory (32, 32a). In addition an analyte is applied to the sensor for measurement and a compensated value is determined for the analyte. Two or more analytes can be measured using the apparatus (1). Sensors are provided for different substances. Many sensors are arranged in at least one dimension. The analyte has an extent covering at least part of the arrangement. At least one value of the analytes is measured by the sensors. The values are spatially resolved over the dimension(s). The electrical value is a voltage, resistance, current, capacity and/or an inductance, or a combination of these. At least one sensor is a field effect transistor (17). The electrical value is the difference between measured- and expected potentials at a terminal of the FET (17). The electrical value is a capacity, inductance or impedance between two electrodes of the sensor, following application of the substance. The correction value is applied to analyte measurements by computer. Alternatively, the correction value is used to influence sensors, hence eliminating a calibration difference during analyte measurements.
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公开(公告)号:DE10015816A1
公开(公告)日:2001-10-18
申请号:DE10015816
申请日:2000-03-30
Applicant: INFINEON TECHNOLOGIES AG
Inventor: FREY ALEXANDER , THEWES ROLAND
IPC: G01N33/53 , C12M1/00 , C12N15/09 , G01N27/327 , G01N27/416 , G01N33/543 , C12Q1/00 , B01L3/00 , G01N33/483
Abstract: The invention relates to a biosensor chip that is provided with a first electrode and a second electrode. The first electrode is provided with a holding area for holding probe molecules which can bind macromolecular biopolymers. The invention also relates to an integrated electric differentiating circuit by means of which an electric current can be detected and can be differentiated according to time, whereby said current is generated during a reduction/oxidation recycling procedure.
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公开(公告)号:DE59704459D1
公开(公告)日:2001-10-04
申请号:DE59704459
申请日:1997-05-21
Applicant: INFINEON TECHNOLOGIES AG
Inventor: KOPLEY THOMAS , WEBER WERNER , THEWES ROLAND
IPC: G11C11/409 , G11C11/4091
Abstract: PCT No. PCT/DE97/01027 Sec. 371 Date Nov. 12, 1998 Sec. 102(e) Date Nov. 12, 1998 PCT Filed May 21, 1997 PCT Pub. No. WO97/47010 PCT Pub. Date Dec. 11, 1997In the read amplifier a mismatch of the inception voltages of cross-coupled transistors (M5, M6) of the read amplifier are compensated by four further transistors (M1 . . . M4), whereby a defined equalizing of the bitlines advantageously takes place with these further transistors simultaneously in what is called the equalize phase. The compensation takes place in that the bitline that is connected with the transistor with the lower inception voltage is charged to a higher level in the pre-load phase. This higher bitline level is switched to the gate of the transistor connected with the other bitline. In the evaluation phase the transistor with the higher inception voltage becomes more strongly conductive. Read amplifiers of this sort are most significant for memory generations beginning at 1 Gbit, since the mismatch due to the variation of the input voltages of the transistors can no longer usefully be solved by a correspondingly large gate surface of the cross-coupled transistors in the read amplifier.
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公开(公告)号:DE10001124C1
公开(公告)日:2001-06-07
申请号:DE10001124
申请日:2000-01-13
Applicant: INFINEON TECHNOLOGIES AG
Inventor: BREDERLOW RALF , THEWES ROLAND
Abstract: The circuit has at least one d.c. current and/or at least one DC voltage source associated with at least one MOSFET (T1) for setting a constant working point and at least one periodically oscillating current and/or voltage source associated with at least one MOSFET so tat the working point oscillates about the constant working point to alter the changes in charge at fault points in the oxide of the MOSFET that can lead to 1/f noise.
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