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公开(公告)号：DE69618344D1
公开(公告)日：2002-02-07
申请号：DE69618344
申请日：1996-06-06
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI
Abstract: In a memory device equipped with a redundancy circuit comprising at least one redundancy memory register (RR1-RRn) storing a defective address of a defective memory element and an identifying code (OC0-OC3) suitable for identifying a portion of a matrix of memory elements wherein the defective memory element is located, a circuit for transferring redundancy data of a redundancy circuit inside the memory device is provided. The circuit comprises a shared bus (INTBUS) of signal lines (INTBUSm) provided in the memory device to interconnect a plurality of circuit blocks (100,101,8) of the memory device and for transferring signals between the circuit blocks. The shared bus (INTBUS) can be selectively to the various circuit blocks, and a bus assignment circuit (4,7) associated to the redundancy circuit is provided for assigning, during a prescribed time interval of a read cycle of the memory device, the shared bus (INTBUS) to the redundancy circuit whereby in the prescribed time interval the identifying code (OC0-OC3) stored in the redundancy memory register can be transferred onto the shared bus (INTBUS).
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公开(公告)号：DE69616019D1
公开(公告)日：2001-11-22
申请号：DE69616019
申请日：1996-03-29
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI
IPC: H02M3/07
Abstract: A voltage booster stage (2) including a voltage booster circuit (10); a generating circuit (12) generating an enabling signal (LSP) enabling the voltage booster circuit; and a control circuit (14) controlling the generating circuit. The control circuit (14) receives a standby signal (ENB), and presents combinatorial logics (44-55) generating an operating mode signal (SPn) having a first value indicating a voltage boost operating mode, and a second value indicating a supply voltage operating mode. The generating circuit (12) receives the operating mode signal (SPn) and the standby signal (ENB), and generates the enabling signal (LSP) enabling the voltage booster circuit in the presence of the standby signal (ENB) and the first value of the operating mode signal (SPn).
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公开(公告)号：DE69521493T2
公开(公告)日：2001-10-11
申请号：DE69521493
申请日：1995-04-04
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI
Abstract: A coding device including an array of multibit registers, each being composed of a plurality of programmable nonvolatile memory cells connected in an OR configuration to a common sensing line of the register to which a single reading circuit is associated. A first, select/enable bus (SELbus) controls the connection of only one at a time of said programmable memory cells to said common sensing line of each multibit register. To each wire of a second, configuring bus (CODE bus) are connected in common the current terminals of as many programming transistors as the memory cells that compose each register, and to each wire of a third, contingently programming bus (PG bus) are connected the gates of the programming transistors of memory cells of the same order of said registers.
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公开(公告)号：ITMI20011150D0
公开(公告)日：2001-05-30
申请号：ITMI20011150
申请日：2001-05-30
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI
IPC: G11C7/10 , G11C16/04 , H01L27/115
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公开(公告)号：DE69520494D1
公开(公告)日：2001-05-03
申请号：DE69520494
申请日：1995-08-04
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI
Abstract: A threshold detecting device (1) comprising a detecting stage (16) having a first input (17) supplied with a monitored voltage (Vb) varying between a first and second value, a second input (15) supplied with a reference voltage (V1) by a reference source stage (8), and an output (18) supplying a logic signal (LA) indicating crossover of a predetermined threshold by the monitored voltage. Initially, the reference source stage (8) is off and the reference voltage (V1) follows the course of the monitored voltage; upon the monitored voltage exceeding a first threshold value, the reference source (8) is turned on and causes the reference voltage (V1) to rise more slowly than the monitored voltage (Vb), so that an increasing voltage difference is present between the first and second inputs (17, 15) of the reference stage; and, upon the voltage difference exceeding a second threshold value, the detecting stage (16) switches and generates the threshold crossover signal (LA).
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Patent Agency Ranking
公开(公告)号：DE69517807T2
公开(公告)日：2001-02-15
申请号：DE69517807
申请日：1995-07-28
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI
IPC: G11C11/4091 , G11C11/409
Abstract: A modulated slope signal generation circuit, particularly for latch data sensing arrangements, having the particularity of comprising: a line (Vmod) for the equalization of a latch arrangement; a branch (13, 14) for following the current of a base cell applied to one of the loads of the latch arrangement; a branch (6, 7) for the slow discharge of the equalization line; a branch (11) for the fast discharge of the equalization line; a branch (2, 3) for evaluating the ratio between a current (ICELLA) that is a function of the conductivity of the cell and a reference current (IREF) that is present on the evaluation branch; and a control signal (PCn) that is sent to the slow discharge branch (6, 7) and to the current follower branch (13, 14); the slow discharge branch (6, 7) being adapted to control a first slope of the signal of the equalization line; the evaluation branch being adapted to control the modulation of the signal of the equalization line, determining its slope change point; the fast discharge branch being adapted to determine a second slope of the signal of the equalization line after the first slope; the first slope of the equalization signal corresponding to a step for the evaluation of a datum and the second slope corresponding to a step for the capture of the datum in the cell.
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公开(公告)号：DE69425367D1
公开(公告)日：2000-08-31
申请号：DE69425367
申请日：1994-04-19
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI , GOLLA CARLA MARIA , MACCARRONE MARCO
Abstract: A read circuit (1) comprising at least one array branch (2) connected to at least one bit line (5), and a reference branch (3) connected to a reference line (11). The array and reference branches each comprise a precharge circuit (4, 10) and load (8, 13, 15) interposed between the supply (7) and the bit line (5) and reference line (11) respectively. The reference load (13, 15) is so formed as to generate a reference current which, during evaluation, is twice the current supplied to the bit line (5). The reference line (11) is connected to an extra-current transistor (43) which is only turned on during equalization so that, during equalization, the selected bit line (5) is supplied with a high current approximating that supplied to the reference line (11). As such, if the cell to be read (6) is written, the output voltage of the array branch (2) is brought rapidly to its natural high value; whereas, if the cell to be read is erased, the output voltage may return to its low value when the extra-current transistor is turned off, thus permitting reading in advance.
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公开(公告)号：DE69517807D1
公开(公告)日：2000-08-10
申请号：DE69517807
申请日：1995-07-28
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI
IPC: G11C11/4091 , G11C11/409
Abstract: A modulated slope signal generation circuit, particularly for latch data sensing arrangements, having the particularity of comprising: a line (Vmod) for the equalization of a latch arrangement; a branch (13, 14) for following the current of a base cell applied to one of the loads of the latch arrangement; a branch (6, 7) for the slow discharge of the equalization line; a branch (11) for the fast discharge of the equalization line; a branch (2, 3) for evaluating the ratio between a current (ICELLA) that is a function of the conductivity of the cell and a reference current (IREF) that is present on the evaluation branch; and a control signal (PCn) that is sent to the slow discharge branch (6, 7) and to the current follower branch (13, 14); the slow discharge branch (6, 7) being adapted to control a first slope of the signal of the equalization line; the evaluation branch being adapted to control the modulation of the signal of the equalization line, determining its slope change point; the fast discharge branch being adapted to determine a second slope of the signal of the equalization line after the first slope; the first slope of the equalization signal corresponding to a step for the evaluation of a datum and the second slope corresponding to a step for the capture of the datum in the cell.
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公开(公告)号：DE69424860D1
公开(公告)日：2000-07-13
申请号：DE69424860
申请日：1994-02-18
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI , GOLLA CARLA MARIA
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公开(公告)号：DE69424523D1
公开(公告)日：2000-06-21
申请号：DE69424523
申请日：1994-02-18
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI , OLIVO MARCO , GOLLA CARLA MARIA
Abstract: A circuit (1) generates flexible timing permitting a slow or fast overall timing configuration, and two configurations of the precharge and detecting intervals by providing both with two (short or long) duration levels. For this purpose, the circuit (1) includes a variable, asymmetrical propagation line (5, 37) composed of a succession of elementary delay elements (6-8, 38, 40) enabled or disabled on the basis of memorized logic signals (TIMS, PCS, DETS), the state of which is determined when debugging the memory (100) in which the circuit (1) is implemented.
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