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    Electrochemical Fabrication Methods for Producing Multilayer Structures Including the use of Diamond Machining in the Planarization of Deposits of Material
    71.
    发明申请
    Electrochemical Fabrication Methods for Producing Multilayer Structures Including the use of Diamond Machining in the Planarization of Deposits of Material 审中-公开
    用于生产多层结构的电化学制造方法包括在材料沉积物平面化中使用金刚石加工

    公开(公告)号：US20090020433A1

    公开(公告)日：2009-01-22

    申请号：US12121625

    申请日：2008-05-15

    Applicant: Adam L. Cohen ,  Uri Frodis ,  Michael S. Lockard ,  Ananda H. Kumar ,  Gang Zhang ,  Dennis R. Smalley

    Inventor： Adam L. Cohen ,  Uri Frodis ,  Michael S. Lockard ,  Ananda H. Kumar ,  Gang Zhang ,  Dennis R. Smalley

    IPC: C25D5/48

    CPC classification number: C25D1/003 ,  B81C1/00492 ,  B81C99/0065 ,  B81C2201/0104 ,  B81C2201/0197 ,  C25D5/02 ,  C25D5/022 ,  C25D5/10 ,  C25D21/12 ,  H01L21/2885 ,  H01L21/76885

    Abstract: Electrochemical fabrication methods for forming single and multilayer mesoscale and microscale structures are disclosed which include the use of diamond machining (e.g. fly cutting or turning) to planarize layers. Some embodiments focus on systems of sacrificial and structural materials which are useful in Electrochemical fabrication and which can be diamond machined with minimal tool wear (e.g. Ni—P and Cu, Au and Cu, Cu and Sn, Au and Cu, Au and Sn, and Au and Sn—Pb), where the first material or materials are the structural materials and the second is the sacrificial material). Some embodiments focus on methods for reducing tool wear when using diamond machining to planarize structures being electrochemically fabricated using difficult-to-machine materials (e.g. by depositing difficult to machine material selectively and potentially with little excess plating thickness, and/or pre-machining depositions to within a small increment of desired surface level (e.g. using lapping or a rough cutting operation) and then using diamond fly cutting to complete he process, and/or forming structures or portions of structures from thin walled regions of hard-to-machine material as opposed to wide solid regions of structural material.

    Abstract translation: 公开了用于形成单层和多层中尺度和微结构的电化学制造方法，其包括使用金刚石加工（例如飞切或车削）来平坦化层。 一些实施例集中于可用于电化学制造的牺牲和结构材料的系统，并且可以以最小的工具磨损（例如Ni-P和Cu，Au和Cu，Cu和Sn，Au和Cu，Au和Sn， 和Au和Sn-Pb），其中第一材料或材料是结构材料，第二材料是牺牲材料）。 一些实施例着重于在使用金刚石加工来平面化使用难以加工的材料进行电化学制造的结构（例如，通过沉积难以加工材料选择性且潜在地具有少量多余电镀厚度和/或预加工沉积 到所需表面水平的小增量（例如使用研磨或粗切割操作），然后使用金刚石飞切切割来完成其加工，和/或从硬质材料的薄壁区域形成结构或部分结构 而不是结构材料的宽固体区域。

    Thinning
    73.
    发明申请
    Thinning 审中-公开
    变薄

    公开(公告)号：US20060276008A1

    公开(公告)日：2006-12-07

    申请号：US11143191

    申请日：2005-06-02

    Applicant: Vesa-Pekka Lempinen ,  Jari Makinen ,  Markku Tilli

    Inventor： Vesa-Pekka Lempinen ,  Jari Makinen ,  Markku Tilli

    IPC: H01L29/84 ,  H01L21/30

    CPC classification number: B81C1/00626 ,  B81B2203/0127 ,  B81C2201/0104 ,  Y10T428/24479

    Abstract: A method for thinning a wafer layer to a predetermined thickness comprises two phases of thinning. A first thinning phase and a second thinning phase, wherein the first thinning phase is a preparatory thinning phase and the second thinning phase is a final thinning phase, so performed that the structure comprising silicon meets as thinned the final thickness as predetermined. Such thinned layer in a wafer for instance, can be used in a sensor to be used in normal sized, micromechanical or even nano-sized devices for the device specific sensing applications in electromechanical devices.

    Abstract translation: 将晶片薄层化为预定厚度的方法包括两个稀化阶段。 第一稀化相和第二稀化相，其中所述第一稀化相是预备性稀化相，并且所述第二稀化相是最后的稀化相，因此进行所述包含硅的结构使预定的最终厚度变薄。 例如，晶片中的这种薄化层可以用于传感器中，以用于在机电装置中用于器件特定感测应用的正常尺寸，微机械或甚至纳米尺寸的装置中。

    Method of fabricating a device having a desired non-planar surface or profile and device produced thereby
    76.
    发明授权
    Method of fabricating a device having a desired non-planar surface or profile and device produced thereby 失效
    制造具有期望的非平面表面或轮廓的装置的方法以及由此制造的装置

    公开(公告)号：US06884732B2

    公开(公告)日：2005-04-26

    申请号：US10269256

    申请日：2002-10-11

    Applicant: Khalil Najafi ,  Chou Tsung-Kuan

    Inventor： Khalil Najafi ,  Chou Tsung-Kuan

    IPC: B81C1/00 ,  H01L21/302 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/331

    CPC classification number: B81C1/00103 ,  B81B2203/0392 ,  B81C1/00547 ,  B81C1/00626 ,  B81C2201/0104 ,  B81C2201/0132 ,  B81C2201/0133 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3083 ,  Y10S438/974 ,  Y10S438/977

    Abstract: A method of fabricating a device having a desired non-planar surface or profile and device produced thereby are provided. A silicon wafer is first coated with silicon nitride, patterned, and DRIE to obtain the desired etch profile. Silicon pillars between trenches are then etched using an isotropic wet etch, resulting in a curved well. The wafer is then oxidized to −2 μm to smooth the surface of the well, and to protect the well from an ensuing planarization process. The nitride is then selectively removed, and the wafer surface is planarized by removing the Si left in the field regions using either a maskless DRIE or CMP. Finally, the oxide is etched away to produce a wafer with a curved surface.

    Abstract translation: 提供一种制造具有期望的非平面表面或轮廓的装置的方法以及由此制造的装置。 硅晶片首先用氮化硅，图案化和DRIE涂覆以获得所需的蚀刻轮廓。 然后使用各向同性的湿蚀刻蚀刻沟槽之间的硅柱，得到弯曲的井。 然后将晶片氧化至-2μm以平滑孔的表面，并保护井免受随后的平坦化过程。 然后选择性地去除氮化物，并且通过使用无掩模DRIE或CMP去除场区域中留下的Si来平坦化晶片表面。 最后，将氧化物蚀刻掉以产生具有弯曲表面的晶片。

    Deep groove structure for semiconductors
    77.
    发明授权
    Deep groove structure for semiconductors 失效
    半导体深槽结构

    公开(公告)号：US06025209A

    公开(公告)日：2000-02-15

    申请号：US909090

    申请日：1997-08-12

    Applicant: Dong-Sing Wuu ,  Ten-Hsing Jaw

    Inventor： Dong-Sing Wuu ,  Ten-Hsing Jaw

    IPC: B81B3/00 ,  G01L9/00 ,  G01L9/08 ,  H01L21/465

    CPC classification number: B81C1/00071 ,  B81C1/00047 ,  G01L9/0042 ,  B81B2203/0127 ,  B81C2201/0104

    Abstract: Deep groove structure for semiconductors comprising a semiconductor substrate, a groove or a cavity formed in said semiconductor substrate and a suspending glass membrane formed on the groove or deep cavity, prepared by a flame hydrolysis deposition process. The suspending glass membrane functions as a planarization structure and has surface at the same level of the surface of the semiconductor substrate. The present invention also discloses a method to prepare the deep groove structure.

    Abstract translation: 用于半导体的深槽结构包括半导体衬底，形成在所述半导体衬底中的凹槽或腔，以及通过火焰水解沉积工艺制备的形成在凹槽或深腔上的悬浮玻璃膜。 悬浮玻璃膜用作平坦化结构，并且具有与半导体基板的表面相同水平面的表面。 本发明还公开了一种制备深沟槽结构的方法。

    CMP PROCESS FLOW FOR MEMS
    79.
    发明申请
    CMP PROCESS FLOW FOR MEMS 审中-公开
    CMP的CMP过程流程

    公开(公告)号：WO2011109231A2

    公开(公告)日：2011-09-09

    申请号：PCT/US2011/026167

    申请日：2011-02-25

    Applicant: CAVENDISH KINETICS, INC. ,  LACEY, Joseph Damian Gordon ,  MAGUIRE, Thomas L. ,  JOSHI, Vikram ,  YOST, Dennis J.

    Inventor： LACEY, Joseph Damian Gordon ,  MAGUIRE, Thomas L. ,  JOSHI, Vikram ,  YOST, Dennis J.

    IPC: B81C1/00

    CPC classification number: B81C1/00095 ,  B81B2203/04 ,  B81B2207/07 ,  B81C1/00611 ,  B81C2201/0104

    Abstract: The present invention generally relates to the formation of a micro-electromechanical system (MEMS) cantilever switch in a complementary metal oxide semiconductor (CMOS) back end of the line (BEOL) process. The cantilever switch is formed in electrical communication with a lower electrode in the structure. The lower electrode may be either blanket deposited and patterned or simply deposited in vias or trenches of the underlying structure. The excess material used for the lower electrode is then planarized by chemical mechanical polishing or planarization (CMP). The cantilever switch is then formed over the planarized lower electrode.

    Abstract translation: 本发明一般涉及在线路（BEOL）工艺的互补金属氧化物半导体（CMOS）后端中形成微机电系统（MEMS）悬臂开关。 悬臂开关形成为与结构中的下电极电连通。 下电极可以是毯式沉积和图案化或简单地沉积在底层结构的通孔或沟槽中。 然后通过化学机械抛光或平面化（CMP）将用于下电极的多余材料平坦化。 然后在平坦化的下电极上形成悬臂开关。

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