公开(公告)号：JPS595935Y2

公开(公告)日：1984-02-23

申请号：JP10906179

申请日：1979-08-08

IPC: H01C7/00 ,  H01C13/02 ,  H01L27/01 ,  H05K1/03 ,  H05K1/09 ,  H05K1/16

CPC classification number: H05K1/167 ,  H01C7/003 ,  H01C13/02 ,  H05K1/0306 ,  H05K1/092 ,  H05K2201/10045

公开(公告)号：US20230380057A1

公开(公告)日：2023-11-23

申请号：US18318512

申请日：2023-05-16

Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.

Inventor： Taichi MISAWA ,  Keiji TANAKA

IPC: H05K1/02 ,  H05K3/10 ,  H05K3/12

CPC classification number: H05K1/0274 ,  H05K3/103 ,  H05K3/1258 ,  H05K2201/10045 ,  H05K2201/09981 ,  H05K2201/10121

Abstract: A package for an optical module includes a substrate provided through a side wall in a first direction. The substrate includes a first wiring layer including a first signal terminal, a second signal terminal, and a first ground terminal. The package includes a second wiring layer disposed under the first wiring layer. The second wiring layer includes a first ground pattern and a first insulating layer disposed between the first wiring layer and the second wiring layer, and includes a groove extending along the first direction, the groove being filled with a metal. The groove is provided within the first ground terminal, in a plan view, and the first insulating layer is free of the groove. The first ground terminal is electrically coupled to the first ground pattern through the metal of the groove.

公开(公告)号：US20230210023A1

公开(公告)日：2023-06-29

申请号：US17561439

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Hubert C. George ,  Ravi Pillarisetty ,  JongSeok Park ,  Stefano Pellerano ,  Lester F. Lampert ,  Thomas F. Watson ,  Florian Luthi ,  James S. Clarke

IPC: H01L27/18 ,  H01L39/22 ,  H03H7/38 ,  H01P3/00 ,  H01L39/24 ,  H01L39/04 ,  G06N10/80 ,  H01L23/00 ,  H05K1/18

CPC classification number: H01L27/18 ,  H01L39/228 ,  H03H7/38 ,  H01P3/003 ,  H01L39/24 ,  H01L39/04 ,  H01L39/221 ,  G06N10/80 ,  H01L24/48 ,  H01L24/45 ,  H01L2224/49171 ,  H01L2224/45144 ,  H05K2201/10045 ,  H01L2924/0495 ,  H01L2224/48225 ,  H01L2224/45186 ,  H05K2201/10522 ,  H05K1/18 ,  H01L2224/45147 ,  H01L2224/48153

Abstract: Technologies for radiofrequency optimized interconnects for a quantum processor are disclosed. In the illustrative embodiment, signals are carried in coplanar waveguides on a surface of a quantum processor die. A ground ring surrounds the signals and is connected to the ground conductors of each coplanar waveguide. Wire bonds connect the ground ring to a ground of a circuit board. The wire bonds provide both an electrical connection from the quantum processor die to the circuit board as well as increased thermal coupling between the quantum processor die and the circuit board, increasing cooling of the quantum processor die.

公开(公告)号：US20170250029A1

公开(公告)日：2017-08-31

申请号：US15597105

申请日：2017-05-16

Applicant: ROHM CO., LTD.

Inventor： Hiroki YAMAMOTO ,  Keishi WATANABE ,  Hiroshi TAMAGAWA

IPC: H01G7/06 ,  H01G4/40 ,  H01G2/06

CPC classification number: H01G4/30 ,  H01G2/06 ,  H01G4/005 ,  H01G4/228 ,  H01G4/232 ,  H01G4/40 ,  H01L22/14 ,  H01L22/20 ,  H01L23/5223 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0629 ,  H01L27/0676 ,  H01L27/101 ,  H01L27/2409 ,  H01L28/40 ,  H01L29/66189 ,  H01L29/94 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/0002 ,  H05K1/111 ,  H05K1/162 ,  H05K1/18 ,  H05K1/181 ,  H05K3/3436 ,  H05K2201/10015 ,  H05K2201/10045 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/85399

Abstract: A chip capacitor according to the present invention includes a substrate, a pair of external electrodes formed on the substrate, a capacitor element connected between the pair of external electrodes, and a bidirectional diode connected between the pair of external electrodes and in parallel to the capacitor element. Also, a circuit assembly according to the present invention includes the chip capacitor according to the present invention and a mounting substrate having lands, soldered to the external electrodes, on a mounting surface facing a front surface of the substrate.

公开(公告)号：US09633779B2

公开(公告)日：2017-04-25

申请号：US14456674

申请日：2014-08-11

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Young Ghyu Ahn ,  Byoung Hwa Lee ,  Sang Soo Park ,  Min Cheol Park

IPC: H01G4/30 ,  H01G4/005 ,  H01G4/228 ,  H01F29/00 ,  H03H7/01 ,  H01G4/01 ,  H05K1/11 ,  H01G4/40 ,  H01G4/012 ,  H01G4/232 ,  H01F27/28 ,  H01F27/29 ,  H01F27/40 ,  H01G2/20 ,  H01G4/06 ,  H03H7/00 ,  H01G4/12

CPC classification number: H01F29/00 ,  H01F27/2804 ,  H01F27/292 ,  H01F27/40 ,  H01F2027/2809 ,  H01G4/005 ,  H01G4/01 ,  H01G4/012 ,  H01G4/12 ,  H01G4/1209 ,  H01G4/228 ,  H01G4/232 ,  H01G4/30 ,  H01G4/40 ,  H03H7/0115 ,  H05K1/111 ,  H05K2201/10015 ,  H05K2201/1003 ,  H05K2201/10045 ,  Y02P70/611

Abstract: A composite electronic component may include: a composite body including a capacitor and an inductor coupled to each other, the capacitor having a ceramic body in which dielectric layers and internal electrodes facing each other with the dielectric layers interposed therebetween are stacked, and the inductor having a magnetic body in which magnetic layers having conductive patterns are stacked; an input terminal disposed on a first end surface of the composite body; an output terminal including a first output terminal disposed on a second end surface of the composite body and a second output terminal disposed on any one or more of upper and lower surfaces and a second side surface of the capacitor; and a ground terminal disposed on any one or more of the upper and lower surfaces and a first side surface of the capacitor and connected to the internal electrodes.

公开(公告)号：US20150043185A1

公开(公告)日：2015-02-12

申请号：US14456674

申请日：2014-08-11

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Young Ghyu AHN ,  Byoung Hwa LEE ,  Sang Soo PARK ,  Min Cheol PARK

IPC: H01G17/00 ,  H01G4/12 ,  H05K1/18 ,  H01F27/29 ,  H01F27/24 ,  H01F29/00 ,  H01G4/30 ,  H01G4/228

CPC classification number: H01F29/00 ,  H01F27/2804 ,  H01F27/292 ,  H01F27/40 ,  H01F2027/2809 ,  H01G4/005 ,  H01G4/01 ,  H01G4/012 ,  H01G4/12 ,  H01G4/1209 ,  H01G4/228 ,  H01G4/232 ,  H01G4/30 ,  H01G4/40 ,  H03H7/0115 ,  H05K1/111 ,  H05K2201/10015 ,  H05K2201/1003 ,  H05K2201/10045 ,  Y02P70/611

Abstract: A composite electronic component may include: a composite body including a capacitor and an inductor coupled to each other, the capacitor having a ceramic body in which dielectric layers and internal electrodes facing each other with the dielectric layers interposed therebetween are stacked, and the inductor having a magnetic body in which magnetic layers having conductive patterns are stacked; an input terminal disposed on a first end surface of the composite body; an output terminal including a first output terminal disposed on a second end surface of the composite body and a second output terminal disposed on any one or more of upper and lower surfaces and a second side surface of the capacitor; and a ground terminal disposed on any one or more of the upper and lower surfaces and a first side surface of the capacitor and connected to the internal electrodes.

Abstract translation: 复合电子部件可以包括：复合体，其包括彼此耦合的电容器和电感器，所述电容器具有陶瓷体，所述陶瓷体叠置有介电层和彼此面对的电介质层的内部电极，所述电感器具有 堆叠具有导电图案的磁性层的磁性体; 输入端子，设置在复合体的第一端面上; 输出端子，包括设置在复合体的第二端面上的第一输出端子和设置在电容器的上表面和下表面中的任一个或多个上的第二输出端子和第二侧表面; 以及设置在所述上​​表面和所述下表面中的任一个或多个上的接地端子和所述电容器的第一侧表面并连接到所述内部电极。

公开(公告)号：US07742314B2

公开(公告)日：2010-06-22

申请号：US11513034

申请日：2006-08-31

Applicant: Kazuhiro Urashima ,  Shinji Yuri ,  Manabu Sato ,  Kohki Ogawa

Inventor： Kazuhiro Urashima ,  Shinji Yuri ,  Manabu Sato ,  Kohki Ogawa

IPC: H05K1/11

CPC classification number: H05K1/185 ,  H01G2/06 ,  H01G4/40 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01056 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/351 ,  H05K1/0233 ,  H05K1/0234 ,  H05K3/4602 ,  H05K2201/10045 ,  H05K2201/10674 ,  H05K2201/10712 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A wiring board comprising: a board core (11) having a core main surface (12) and a core reverse surface (13); a capacitor (101, 101A, 101B, 101C, 101D, 101E, 101F, 101G, 101H, 101J, 1101, 1101′, 1101″, 1101′″, 1101″″, 1101′″″) having a capacitor main surface (102) and a capacitor reverse surface (103) and having a structure in which first inner electrode layers (141) and second inner electrode layers (142) are alternately laminated and arranged via a dielectric layer (105), the capacitor (101, 101A, 101B, 101C, 101D, 101E, 101F, 101G, 101H, 101J, 1101, 1101′, 1101″, 1101′″, 1101″″, 1101′″″) being accommodated in the board core (11) in a state in which the core main surface (12) and the capacitor main surface (102) are oriented on a same side; and a wiring laminated portion (31) having a structure in which interlayer insulating layers (33, 35) and conductor layers (42) are alternately laminated on the core main surface (12) and the capacitor main surface (102), wherein an inductor (251, 252, 253) or a resistor (301, 302, 311, 312, 321, 322) is formed on or in the capacitor (101, 101A, 101B, 101C, 101D, 101E, 101F, 101G, 101H, 101J, 1101, 1101′, 1101″, 1101′″, 1101″″, 1101′″″).

Abstract translation: 一种布线板，包括：具有芯主表面（12）和芯反向表面（13）的板芯（11）; 具有电容器主表面的电容器（101,101A，101B，101C，101D，101E，101F，101G，101H，101J，1101,1101,1101,1101“，1101”，1101“”，1101“ 102）和电容器反面（103），并且具有通过电介质层（105）交替层叠配置第一内电极层（141）和第二内电极层（142）的结构，电容器（101,101A ，101B，101C，101D，101E，101F，101G，101H，101J，1101,1101'，1101“，1101”“，1101”“，1101”“）被容纳在板芯（11） 其中所述芯主表面（12）和所述电容器主表面（102）位于同一侧; 以及具有层间绝缘层（33,35）和导体层（42）交替层叠在芯主表面（12）和电容器主表面（102）上的结构的布线层叠部分（31），其中电感器 （101,101A，101B，101C，101D，101E，101F，101G，101H，101J）中的电容器（251,102,253）或电阻器（301,302,311,312,321,322） ，1101,1101'，1101“，1101”“，1101”“，1101”“）。

公开(公告)号：US07715164B2

公开(公告)日：2010-05-11

申请号：US11984559

申请日：2007-11-20

Applicant: Chien-Hao Huang ,  Wen-Chih Li

Inventor： Chien-Hao Huang ,  Wen-Chih Li

IPC: H02H5/04

CPC classification number: H05K1/0234 ,  H05K1/0257 ,  H05K1/0259 ,  H05K1/141 ,  H05K1/167 ,  H05K1/185 ,  H05K3/3442 ,  H05K3/4611 ,  H05K3/4688 ,  H05K2201/09181 ,  H05K2201/09309 ,  H05K2201/10045 ,  Y10T428/239

Abstract: An embedded type multifunctional integrated structure and a method for manufacturing the same are disclosed. The present invention utilizes the concept of multi-layer design to integrated more than two passive components on a component structure that would be adhered to a substrate. Hence, the embedded type multifunctional integrated structure has an OCP function, an OVP function, an anti-EMI function, and an anti-ESD function at the same time. Therefore, the present invention effectively integrated two or more than one passive components in order to increase function of the embedded type multifunctional integrated structure. Moreover, the present invention effectively reduces the size of the passive components on a PCB and reduces the number of solder joints.

Abstract translation: 公开了一种嵌入式多功能一体化结构及其制造方法。 本发明利用多层设计的概念将多于两个的无源部件集成在将粘附到基板上的部件结构上。 因此，嵌入式多功能一体化结构同时具有OCP功能，OVP功能，抗EMI功能和抗ESD功能。 因此，为了增加嵌入式多功能一体化结构的功能，本发明有效地集成了两个或多个无源部件。 此外，本发明有效地减小了PCB上的无源部件的尺寸，并且减少了焊点的数量。

公开(公告)号：US07601920B2

公开(公告)日：2009-10-13

申请号：US10579680

申请日：2004-11-12

Applicant: Koji Fujimoto

Inventor： Koji Fujimoto

IPC: H05K1/02

CPC classification number: H05K3/3442 ,  H01C1/16 ,  H01C13/02 ,  H01C17/006 ,  H01C17/28 ,  H05K2201/10045 ,  Y02P70/613

Abstract: The present invention provides a surface mount composite electronic component which can be made compact. The structure of the surface mount composite electronic component is one in which a circuit element is formed on each of a set of opposing surfaces of an insulating substrate composed of a hexahedron, with electrodes that make up the circuit elements also functioning as external terminals. For example, a pair of first electrodes disposed on both ends of a front surface of the insulating substrate composed of a hexahedron, a pair of second electrodes disposed on a rear surface of the insulating substrate opposite the first electrodes, a first resistor disposed so as to contact both of the first pair of electrodes, and a second resistor disposed so as to contact both of the second electrodes.

Abstract translation: 本发明提供一种可以制成紧凑的表面安装复合电子部件。 表面安装复合电子部件的结构是其中在由六面体组成的绝缘基板的一组相对表面的每一个上形成电路元件的结构，其中构成电路元件的电极也用作外部端子。 例如，设置在由六面体构成的绝缘基板的前表面的两端上的一对第一电极，设置在与第一电极相对的绝缘基板的后表面上的一对第二电极，第一电阻器设置为 以接触第一对电极中的两个，以及设置成接触两个第二电极的第二电阻器。

公开(公告)号：US20080298031A1

公开(公告)日：2008-12-04

申请号：US12119800

申请日：2008-05-13

Applicant: Gheorghe Korony

Inventor： Gheorghe Korony

IPC: H05K1/16 ,  H05K3/00

CPC classification number: H01P1/20 ,  H01L2224/48091 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/16 ,  H05K3/0052 ,  H05K3/403 ,  H05K2201/0317 ,  H05K2201/09154 ,  H05K2201/10045 ,  Y10T29/49155 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Shaped integrated passive devices and corresponding methodologies relate to construction and mounting of shaped passive devices on substrates so as to provide both mechanical and electrical connection. Certain components and component assemblies are associated with the implementation of surface mountable devices. Specially shaped integrated passive device are capable of providing simplified mounting on and simultaneous connection to selected electrical pathways on a printed circuit board or other mounting substrate. Shaped, plated side filter devices have plated sides which provide both mounting and grounding/power coupling functions. Thin film filters may be constructed on silicon wafers, which are then diced from the top surface with an angular dicing saw to produce a shaped groove in the top surface. The groove may be v-shaped or other shape, and is then plated with a conductive material. Individual pieces are separated by grinding the back surface of the wafer down to where the grooves are intercepted. The plated grooves serve as ground or power connection points for the filter circuit. The metallized slopes of the plated grooves are used in securing the individual pieces to a mounting surface, by soldering or using conductive epoxy.

Abstract translation: 形状的集成无源器件和相应的方法涉及在基底上的成形无源器件的结构和安装，以便提供机械和电连接。 某些组件和组件组件与表面可安装设备的实现相关联。 特殊形状的集成无源器件能够简化安装在印刷电路板或其他安装基板上的选定电路上并同时连接。 成型的电镀侧过滤器装置具有电镀侧面，其提供安装和接地/电力耦合功能。 薄膜过滤器可以构造在硅晶片上，然后用角切割锯从顶表面切割，以在顶表面中产生成形凹槽。 凹槽可以是v形或其他形状，然后用导电材料镀覆。 通过将晶片的后表面向下研磨到凹槽被截取的地方分开各个片段。 电镀槽用作滤波电路的接地或电源连接点。 电镀槽的金属化斜坡用于通过焊接或使用导电环氧树脂将各个片固定到安装表面。