EMBEDDED FIRMWARE COPY PREVENTING DEVICE AND FIRMWARE PROTECTING METHOD IN NON-VOLATILE MEMORY DEVICE

    公开(公告)号:JP2001175539A

    公开(公告)日:2001-06-29

    申请号:JP2000339320

    申请日:2000-11-07

    Inventor: TAI-MIN CHEN

    Abstract: PROBLEM TO BE SOLVED: To provide a device and a method for preventing an illegal firmware copy. SOLUTION: In the firmware copy preventing device having a protected memory for storing plural access keys, a first memory position for storing a seed value, a second memory position for storing the estimate value of a first copy prevention function and a third memory position for storing the result of a second copy prevention function, the access key can not be read by system software, the first copy prevention function is the function of the seed value and the first key of the plural access keys and when the first copy prevention function is successful in comparison, the second copy prevention function is the function of the seed value and the second key of the plural access keys.

    CONTROL CIRCUIT FOR LIGHT EMITTING ELEMENT ARRAY

    公开(公告)号:JP2001085984A

    公开(公告)日:2001-03-30

    申请号:JP2000217873

    申请日:2000-07-18

    Abstract: PROBLEM TO BE SOLVED: To realize a control circuit which operates a light emitting elements row with small power and reduces complexity by providing 1st and 2nd current sources connected to a 1st column circuit connected to the light emitting elements. SOLUTION: A drive circuit for the column line 20 to which the light emitting elements 23 to 27 are connected consists of a current source 15, a comparator 16, a current source 14 and a transistor 17. A large current is supplied at a start of each of column cycles by adding to the large current source 15 to charge the column up to a prescribed voltage. A reference voltage corresponding to the prescribed voltage is applied to a reference voltage line 12 during a charging period, once the voltage reaches the prescribed voltage, the comparator 16 disconnects the source 15. Next, the source 15 supplies a 'quick charge' current to charge the capacitor of an active light emitting element in the column, and supplies a desired pixel current when inheritance to the source 14 becomes available. Thus, the source supplies sufficient current and the active light emitting elements emit light in most of the column cycles.

    FLATTENING METHOD OF POLYMER LAYER
    84.
    发明专利

    公开(公告)号:JP2001077064A

    公开(公告)日:2001-03-23

    申请号:JP2000210311

    申请日:2000-07-11

    Abstract: PROBLEM TO BE SOLVED: To enable a polymer layer such as a resist layer on a substrate to be flattened by a method wherein the polymer layer is made very selective to a dielectric layer exposed to an abrasive composition to use when the polymer layer is chemically, mechanically polished. SOLUTION: A polymer layer which contains photoresist is flattened through a chemical mechanical polishing method. An abrasive composition used in this case is very selective to a dielectric layer, and especially its selection ratio to a silicon nitride layer is about 10:1, preferably at least about 1000:1. This composition is at least of pH 8 or so, preferably pH 11 to 13 or so. A typical abrasive composition can contain abrasive material such as silica or alumina basic solution. A oxidizing component resides as much as 2 wt.%, an abrasive composition can contain a strong base and requires no oxidizing agent or no abrasive material. A proper strong base contains a hydroxide such as a trimethyl ammonium hydroxide or sodium hydroxide.

    SYNCHRONOUS CLOCK FOR GENERATING CIRCUIT

    公开(公告)号:JP2000354029A

    公开(公告)日:2000-12-19

    申请号:JP2000094511

    申请日:2000-03-30

    Abstract: PROBLEM TO BE SOLVED: To minimize a board space and to obtain a stable synchronous signal of high quality by generating a synchronous signal which marks a prescribed side edge for an internal clock having its phase matched with that of an external system clock. SOLUTION: An external system clock is supplied to a subsystem called a 'master' 24 among plural subsystems 22. The master 24 includes a voltage- controlled oscillator(VCO), which has the frequency equal to a multiple of the external system clock and generates a VCO clock signal, having its frequency matched with that of the external system clock. An internal system clock is generated in the master 24 and has the frequency which is equal to that of the external system clock and is matched with the phase of the VCO clock signal. Then the master 24 generates a synchronous signal which marks a prescribed side edge of the internal clock signal. The VCO clock signal, which functions to secure the synchronization of all subsystems 22, is supplied to every subsystem 22 so as to make these clock signals arrive at the same phase.

    TRANSISTOR EQUIPPED WITH EMBEDDED STRAP CONNECTED TO MEMORY DEVICE

    公开(公告)号:JP2000353795A

    公开(公告)日:2000-12-19

    申请号:JP2000139018

    申请日:2000-05-11

    Abstract: PROBLEM TO BE SOLVED: To obtain a method of manufacturing an LSI which contains a vertical transistor and is lessened in size, provided at a low cost, and enhanced in reliability. SOLUTION: A capacitor 41 composed of a trench 13, an insulating film 14, and a conductor 16 is formed in a substrate 10, and a stepped part is provided at the upper part of an opening 50 bored in the substrate 10, and then the opening 50 is filled with insulator for the formation of an isolation region 50. The upper part of the stepped part is filled with a conductive material to serve as a strap 904, and N-type ions are implanted for the formation of a source region 61 inside the substrate 10. An insulating film 905 is attached, a gate electrode 108 is deposited, a trench 105 is cut by etching, a spacer 103 is attached, then N-type ions are implanted to form a drain region 106 adjacent to the upper gate 108, and the opening 105 is filled up with conductor to serve as a contact. The strap 904 serves as a source electrode which crosses the capacitor 41 at grade and is electrically connected to the contact 105, which serves as a drain electrode through the intermediary of diffusion regions 61 and 106 located inside the substrate 10.

    METHOD AND PROCESS FOR GENERATING TRENCH CELL CAPACITOR IN SEMICONDUCTOR SUBSTRATE, AND FORMING METHOD OF TRENCH CAPACITOR

    公开(公告)号:JP2000294747A

    公开(公告)日:2000-10-20

    申请号:JP2000094512

    申请日:2000-03-30

    Abstract: PROBLEM TO BE SOLVED: To prevent dislocation owing to a stack defect and the occurrence of stress by lining a trench formed in a semiconductor substrate in a dielectric layer, installing a nitride layer on oxide formed on an upper part and filling a collar with a trench semiconductor material. SOLUTION: DRAM formed on a semiconductor substrate 33 doped by epitaxial growth has a transistor 36 and a trench capacitor 32 accumulating data. The trench capacitor 32 is provided with a trench cell 21 and is provided with a thick oxide isolation collar 24 formed at a periphery along an upper sidewall. A thin nitride liner 25 is arranged on the inner sidewall of the oxide collar 24. A buried layer is doped in high density and is formed in a substrate 33 by selective ion implantation. The buried layer and the channel area 28 of the transistor 36 are separated by a depth line 43. The transistor 36 is formed of a drain well 23, a source well 29 and a gate 35.

    SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF

    公开(公告)号:JP2000260729A

    公开(公告)日:2000-09-22

    申请号:JP2000056273

    申请日:2000-03-01

    Abstract: PROBLEM TO BE SOLVED: To provide a simple semiconductor device manufacturing method, with which a doped configuration can be realized which is substantially equal to the conventional device using a single mask. SOLUTION: In this method, wherein a conductive type embedded layer 19, at least the part of which reaches to the surface of a layer 12, is formed in a conductive type semiconductor region, the embedded layer 19 is formed by implanting conductive type ions into the embedded layer 19 through the opening part of an implanting mask having a tapered edge. However, the implanted layer has a tapered part and the tapered edge has an opening part, so that the tapered part is set so as to correspond to the tapered edge of the mask.

    PRODUCTION OF PHOTOLITHOGRAPHIC STRUCTURE

    公开(公告)号:JP2000241989A

    公开(公告)日:2000-09-08

    申请号:JP2000038346

    申请日:2000-02-16

    Abstract: PROBLEM TO BE SOLVED: To easily produce a photolithographic structure suitable for patterning in a far UV range. SOLUTION: A photoresist containing a base resin containing a protected active part that forms a reactive part under deprotection and a photoactive component readily sensitive to actinic radiation is applied to a substrate, patternwise exposed with an effective dose of the actinic radiation and exposed to a developer to form a patterned photoresist. The protected active part of the base resin is then deprotected to chemically form a reactive part, this reactive part is allowed to react with an aromatic ring-containing etch protector to incorporate the etch protector into the base resin and the substrate is etched.

    DYNAMIC RANDOM ACCESS MEMORY AND MANUFACTURE OF THE SAME

    公开(公告)号:JP2000196045A

    公开(公告)日:2000-07-14

    申请号:JP37569999

    申请日:1999-12-28

    Abstract: PROBLEM TO BE SOLVED: To obtain necessary insulation between a capacitor for storage and a transistor in a memory cell, using both a capacitor for storage in a vertical trench and a vertical transistor. SOLUTION: One memory cell formed in a semiconductor main body 10 includes a polycrystalline silicon packing part 22 as a capacitor for storage and one field-effect transistor. This field-effect transistor includes a source 43 formed in the sidewall of a trench, a drain 42 formed in the semiconductor main body and provided with a surface in common with the upper face of the semiconductor main body, a channel region including both vertical and horizontal parts, and a polycrystalline silicon gate at the upper part of the trench. Thus, an insulating oxide layer 28 at the top end of the polycrystalline silicon packing part, which is useful as a storage node and the polycrystalline silicon packing part which is useful as a gate conductor can be obtained in this process for manufacturing.

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