公开(公告)号：US20190229182A1

公开(公告)日：2019-07-25

申请号：US15539478

申请日：2016-12-28

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Shengkai Wang ,  Honggang Liu ,  Bing Sun ,  Hudong Chang

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: The present disclosure relates to the field of semiconductor Integrated Circuit (IC) manufacture, and provides an InGaAs-based double-gate PMOS Field Effect Transistor (FET). The FET includes a bottom gate electrode, a bottom gate dielectric layer, a bottom gate interface control layer, an InGaAs channel layer, an upper interface control layer, a highly doped P-type GaAs layer, an ohmic contact layer, source/drain metal electrodes, a top gate dielectric layer and a top gate electrode. The source/drain metal electrodes are located on opposite sides of the ohmic contact layer. A gate trench structure is etched to an upper surface of the interface control layer between the source and drain metal electrodes. The top gate dielectric layer uniformly covers an inner surface of the gate trench structure, and the top gate electrode is provided on the top gate dielectric layer. The present disclosure provides a PMOS FET with better gate control functionality and a low interface density with the double-gate structure and interface control layer design, in order to meet the requirements of high-performance PMOS transistors.

公开(公告)号：US10312345B2

公开(公告)日：2019-06-04

申请号：US15871690

申请日：2018-01-15

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Jinjuan Xiang ,  Xiaolei Wang ,  Hong Yang ,  Shi Liu ,  Junfeng Li ,  Wenwu Wang ,  Chao Zhao

IPC: H01L21/3205 ,  H01L29/66 ,  H01L21/265 ,  H01L29/49

Abstract: The present disclosure provides a method for manufacturing a transistor having a gate with a variable work function, comprising: providing a semiconductor substrate; forming a dummy gate stack on the semiconductor substrate and performing ion implantation on an exposed area of the semiconductor substrate at both sides of the dummy gate stack to form source/drain regions; removing the dummy gate and annealing the source/drain regions; providing an atomic layer deposition reaction device; introducing a precursor source reactant into the atomic layer deposition reaction device; and controlling an environmental factor for the atomic layer deposition device to grow a work function metal layer. The present disclosure also provides a transistor having a gate with a variable work function. The present disclosure may adjust a variable work function, and may use the same material system to obtain an adjustable threshold voltage within an adjustable range.

公开(公告)号：US20190139831A1

公开(公告)日：2019-05-09

申请号：US16222570

申请日：2018-12-17

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong ZHU

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L21/762 ,  H01L21/308

CPC classification number: H01L21/823481 ,  H01L21/26513 ,  H01L21/26533 ,  H01L21/26586 ,  H01L21/3081 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Semiconductor arrangements and methods of manufacturing the same. The semiconductor arrangement may include: a substrate including a base substrate, a first semiconductor layer on the substrate, and a second semiconductor layer on the first semiconductor layer; first and second fin structures formed on the substrate and extending in the same straight line, each of the first and second fin structures including at least portions of the second semiconductor layer; a first isolation part formed around the first and second fin structures on opposite sides of the straight line; first and second FinFETs formed on the substrate based on the first and second fin structures respectively; and a second isolation part between the first and second fin structures and intersecting the first and second fin structures to isolate the first and second fin structures from each other.

公开(公告)号：US10263111B2

公开(公告)日：2019-04-16

申请号：US14647736

申请日：2012-12-07

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huilong Zhu ,  Miao Xu

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L21/311 ,  H01L21/02 ,  H01L21/308 ,  H01L29/08 ,  H01L21/265 ,  H01L29/165

Abstract: A FinFET and a method for manufacturing the same are provided. The method includes: patterning a semiconductor substrate to form a ridge; performing ion implantation such that a doped punch-through-stopper layer is formed in the ridge and a semiconductor fin is formed by a portion of the semiconductor substrate disposed above the doped punch-through-stopper layer; forming a gate stack intersecting the semiconductor fin, the gate stack comprising a gate conductor and a gate dielectric isolating the gate conductor from the semiconductor fin; forming a gate spacer surrounding the gate conductor; and forming source and drain regions in portions of the semiconductor fin at opposite sides of the gate stack.

公开(公告)号：US20190074363A1

公开(公告)日：2019-03-07

申请号：US16123016

申请日：2018-09-06

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu

IPC: H01L29/423 ,  H01L27/108 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11582 ,  H01L27/11587 ,  H01L27/1159 ,  H01L27/11597 ,  H01L29/78

Abstract: A semiconductor memory device that may include a substrate, an array of memory cells arranged in rows and columns, bit lines and word lines. The memory cells each may include a pillar-shaped active region extending vertically, which includes source/drain regions at upper and lower ends respectively and a channel region between the source/drain regions. The channel region may include a single-crystalline semiconductor material. The memory cells each may further include a gate stack formed around a periphery of the channel region. Each of the bit lines is located below a corresponding column, and electrically connected to the lower source/drain regions of the respective memory cells in the corresponding column. Each of the word lines is electrically connected to the gate stacks of the respective memory cells in a corresponding row.

公开(公告)号：US10176287B2

公开(公告)日：2019-01-08

申请号：US14403938

申请日：2014-04-25

Applicant: The Institute of Microelectronics of Chinese Academy of Sciences

Inventor： Jianhui Bu ,  Shuzhen Li ,  Jiajun Luo ,  Zhengsheng Han

IPC: G06F17/50

Abstract: The invention discloses an STI stress effect modeling method and device of an MOS device, and belongs to the technical field of parameter extraction modeling of devices. The method comprises the following steps: introducing the influence of temperature parameters on the STI stress effect of the MOS device, so as to form a function showing that the STI stress effect of the MOS device changes along with the temperature parameters; extracting the model parameter Model1 of the MOS device at normal temperature; on the basis of the Model1, extracting the parameter Model2 that the STI stress affects the properties of the MOS device at normal temperature; and on the basis of the Model2, extracting fitting parameters of the MOS device in the function so as to acquire final model parameters. The device comprises a first module, a second module, a third module and a fourth module. By establishing the function showing that the STI stress effect of the MOS device changes along with the temperature parameters, the influence of the temperature on the STI stress effect of the MOS device can be accurately described, so that the extracted model parameters are more accurate and reliable.

公开(公告)号：US20180315484A1

公开(公告)日：2018-11-01

申请号：US15769619

申请日：2015-11-23

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Tianchun Ye

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/08

CPC classification number: G11C16/08

Abstract: A method for operating a semiconductor memory includes: randomizing a data of an operation address to obtain a random code; performing a combinational logic operation between the random code and the original data to obtain a randomized data, or performing a combinational logic operation between the randomized data and the random code to obtain a de-randomized data; saving the randomized data, or outputting the de-randomized data. According to the method for operating a semiconductor memory of the present invention, since a combinational logic or a non-iterative sequential logic is used to form a random sequence generation unit, the encoding/decoding process does not need to wait for a specific cycle, thus reducing the operation time and improving the chip performance.

公开(公告)号：US20180261625A1

公开(公告)日：2018-09-13

申请号：US15758292

申请日：2015-11-23

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Zongliang HUO ,  Tianchun YE

IPC: H01L27/11582 ,  H01L21/308 ,  H01L21/306 ,  H01L21/762 ,  H01L21/02 ,  H01L21/027 ,  H01L21/311 ,  H01L29/10 ,  H01L21/28

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/02636 ,  H01L21/0274 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/31111 ,  H01L21/762 ,  H01L21/76224 ,  H01L29/1037 ,  H01L29/40117 ,  H01L29/66545 ,  H01L29/66833 ,  H01L29/7926

Abstract: A three-dimensional memory device and method of manufacturing the same, an isolation structure is embedded between the common source region and the substrate thereunder, which can inhibit the undesired diffusion of impurities during the implantation of the common source region, avoiding operation failure due to excessive diffusion of impurities. In programming and reading states of the three-dimensional memory device, electrons flow from the common source region to bit line; while in erase states, holes are injected from the substrate. Due to the isolation structure, the three-dimensional memory device achieves spatial separation of electrons from holes required for programming/erasing, improving the erasing efficiency and the integration as well.

公开(公告)号：US10043909B2

公开(公告)日：2018-08-07

申请号：US15368629

申请日：2016-12-04

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/06 ,  H01L29/165 ,  H01L29/20 ,  H01L29/66 ,  H01L21/311

Abstract: A semiconductor device with a high-quality epitaxial layer and a method of manufacturing the same. The semiconductor device may include: a substrate; a fin-shaped first semiconductor layer spaced apart from the substrate; a second semiconductor layer at least partially surrounding a periphery of the first semiconductor layer; an isolation layer formed on the substrate, exposing at least a part of the second semiconductor layer, wherein the exposed part of the second semiconductor layer extends in a fin shape; and a gate stack formed on the isolation layer and intersecting the second semiconductor layer.

公开(公告)号：US20180197993A1

公开(公告)日：2018-07-12

申请号：US15849217

申请日：2017-12-20

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Jun LUO ,  Chao ZHAO ,  Shi LIU

IPC: H01L29/78 ,  H01L29/45 ,  H01L29/167 ,  H01L29/66 ,  H01L21/311 ,  H01L21/265 ,  H01L21/285 ,  H01L21/321

CPC classification number: H01L29/7851 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76855 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66795

Abstract: The present invention relates to a semiconductor device and a method of manufacturing the same. There is provided a semiconductor device comprising: a semiconductor substrate with a fin; a gate intersecting with the fin and a source region and a drain region within the fin at both sides of the gate; metal silicides formed at the source region and the drain region and in contact with the source region and the drain region respectively; wherein there is a impurity dopant at a interface of the metal silicide in contact with the source/drain region, which is capable of reducing a Schottky barrier height between the metal silicide and the source/drain region. The provided semiconductor device can reduce the Schottky barrier height between the metal silicide and the source/drain region, thereby reducing the specific resistance of the contact.