公开(公告)号：US10312345B2

公开(公告)日：2019-06-04

申请号：US15871690

申请日：2018-01-15

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Jinjuan Xiang ,  Xiaolei Wang ,  Hong Yang ,  Shi Liu ,  Junfeng Li ,  Wenwu Wang ,  Chao Zhao

IPC: H01L21/3205 ,  H01L29/66 ,  H01L21/265 ,  H01L29/49

Abstract: The present disclosure provides a method for manufacturing a transistor having a gate with a variable work function, comprising: providing a semiconductor substrate; forming a dummy gate stack on the semiconductor substrate and performing ion implantation on an exposed area of the semiconductor substrate at both sides of the dummy gate stack to form source/drain regions; removing the dummy gate and annealing the source/drain regions; providing an atomic layer deposition reaction device; introducing a precursor source reactant into the atomic layer deposition reaction device; and controlling an environmental factor for the atomic layer deposition device to grow a work function metal layer. The present disclosure also provides a transistor having a gate with a variable work function. The present disclosure may adjust a variable work function, and may use the same material system to obtain an adjustable threshold voltage within an adjustable range.

公开(公告)号：US20150255557A1

公开(公告)日：2015-09-10

申请号：US14722684

申请日：2015-05-27

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu ,  Qiuxia Xu ,  Yanbo Zhang ,  Hong Yang

IPC: H01L29/423 ,  H01L21/8238 ,  H01L21/265 ,  H01L29/45 ,  H01L27/092 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L29/42372 ,  H01L21/2652 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/0924 ,  H01L29/1083 ,  H01L29/45 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor device and a method of manufacturing the same are disclosed. The method includes forming a semiconductor fin on a semiconductor substrate. The method further includes forming an interfacial oxide layer on a top surface and sidewalls of the semiconductor fin. The method further includes forming a high K gate dielectric layer on the interfacial oxide layer. The method further includes forming a first metal gate layer on the high K gate dielectric layer. The method further includes implanting dopant to the first metal gate layer through conformal doping. The method further includes performing annealing so that the dopants are diffused and accumulated at an upper interface between the high K gate dielectric layer and the first metal gate layer, as well as at a lower interface between the high K gate dielectric layer and the interfacial oxide layer, generating electrical dipoles at the lower interface through interfacial reaction.

Abstract translation: 公开了一种半导体器件及其制造方法。 该方法包括在半导体衬底上形成半导体鳍片。 该方法还包括在半导体鳍片的顶表面和侧壁上形成界面氧化物层。 该方法还包括在界面氧化物层上形成高K栅极电介质层。 该方法还包括在高K栅介质层上形成第一金属栅极层。 该方法还包括通过共形掺杂将掺杂剂注入第一金属栅极层。 该方法还包括执行退火，使得掺杂剂在高K栅极介电层和第一金属栅极层之间以及在高K栅极介电层和界面氧化物之间的较低界面处扩散和积聚 层，通过界面反应在下界面产生电偶极子。

公开(公告)号：US20150041925A1

公开(公告)日：2015-02-12

申请号：US14385101

申请日：2012-12-07

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huilong Zhu ,  Qiuxia Xu ,  Yanbo Zhang ,  Hong Yang

IPC: H01L21/28 ,  H01L29/78 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L21/266

CPC classification number: H01L21/28008 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/268 ,  H01L21/28088 ,  H01L21/28167 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/78 ,  H01L29/7833

Abstract: Provided are P type MOSFETs and methods for manufacturing the same. The method may include forming source/drain regions in a semiconductor substrate; forming an interfacial oxide layer on the semiconductor substrate; forming a high K gate dielectric layer on the interfacial oxide layer; forming a first metal gate layer on the high K gate dielectric layer; implanting dopants into the first metal gate layer through conformal doping; and performing annealing to change an effective work function of a gate stack including the first metal gate layer, the high K gate dielectric, and the interfacial oxide layer.

Abstract translation: 提供P型MOSFET及其制造方法。 该方法可以包括在半导体衬底中形成源极/漏极区域; 在所述半导体衬底上形成界面氧化物层; 在界面氧化物层上形成高K栅介电层; 在所述高K栅极电介质层上形成第一金属栅极层; 通过共形掺杂将掺杂剂注入第一金属栅极层; 并执行退火以改变包括第一金属栅极层，高K栅极电介质和界面氧化物层的栅极堆叠的有效功函数。

公开(公告)号：US10056261B2

公开(公告)日：2018-08-21

申请号：US14385101

申请日：2012-12-07

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huilong Zhu ,  Qiuxia Xu ,  Yanbo Zhang ,  Hong Yang

IPC: H01L21/28 ,  H01L21/266 ,  H01L29/78 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L21/265 ,  H01L21/268

CPC classification number: H01L21/28008 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/268 ,  H01L21/28088 ,  H01L21/28167 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/78 ,  H01L29/7833

Abstract: Provided are P type MOSFETs and methods for manufacturing the same. The method may include forming source/drain regions in a semiconductor substrate; forming an interfacial oxide layer on the semiconductor substrate; forming a high K gate dielectric layer on the interfacial oxide layer; forming a first metal gate layer on the high K gate dielectric layer; implanting dopants into the first metal gate layer through conformal doping; and performing annealing to change an effective work function of a gate stack including the first metal gate layer, the high K gate dielectric, and the interfacial oxide layer.

公开(公告)号：US09934975B2

公开(公告)日：2018-04-03

申请号：US14494447

申请日：2014-09-23

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu ,  Qiuxia Xu ,  Yanbo Zhang ,  Hong Yang

IPC: H01L21/28 ,  H01L29/66 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L21/28105 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28185 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/66545

Abstract: An N-type MOSFET and a method for manufacturing the same are disclosed. In one aspect, the method comprises forming source/drain regions in a semiconductor substrate. The method also includes forming an interfacial oxide layer on the semiconductor substrate. The method also includes forming a high-k gate dielectric layer on the interfacial oxide layer. The method also includes forming a first metal gate layer on the high-k gate dielectric layer. The method also includes implanting dopants into the first metal gate layer through conformal doping. The method also includes annealing a gate stack to change an effective work function of the gate stack which includes the first metal gate layer, the high-k gate dielectric, and the interfacial oxide layer.

公开(公告)号：US09373622B2

公开(公告)日：2016-06-21

申请号：US14721386

申请日：2015-05-26

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huaxiang Yin ,  Hong Yang ,  Qingzhu Zhang ,  Qiuxia Xu

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L27/092 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L27/0924

Abstract: An CMOS device comprises a plurality of NMOS transistors and a plurality of PMOS transistors, each of which comprises a gate stack constituted of a gate insulating layer and a gate metal layer on a substrate, a source/drain region in the substrate on both sides of the gate stack and a channel region below the gate stack, wherein the gate metal layer of each NMOS transistor comprising a first barrier layer, an NMOS work function adjusting layer, a second barrier layer, and a filling layer, and wherein the gate metal layer of each PMOS transistor comprising a first barrier layer, a PMOS work function adjusting layer, an NMOS work function adjusting layer, a second barrier layer, and a filling layer, and wherein the first barrier layer in the gate metal layer of the NMOS transistor and the first barrier layer in the gate metal layer of the PMOS transistor contain a doping ion to finely adjust the work function. The semiconductor device and the method for manufacturing the same according to the present disclosure utilize the sacrificial layer to diffuse impurity to the barrier layer so that the adjusting accuracy of the threshold voltage may be effectively improved, thereby facilitating in improving the whole performance of the device.

Abstract translation: CMOS器件包括多个NMOS晶体管和多个PMOS晶体管，每个PMOS晶体管包括由衬底上的栅极绝缘层和栅极金属层构成的栅极堆叠，在衬底的两侧的衬底中的源极/漏极区域 栅极堆叠和栅极堆叠下方的沟道区，其中每个NMOS晶体管的栅极金属层包括第一势垒层，NMOS功函数调节层，第二势垒层和填充层，并且其中栅极金属层 每个PMOS晶体管包括第一阻挡层，PMOS功函数调整层，NMOS功函数调整层，第二势垒层和填充层，并且其中NMOS晶体管的栅极金属层中的第一势垒层和 PMOS晶体管的栅极金属层中的第一势垒层含有掺杂离子以微调功函数。 根据本公开的半导体器件及其制造方法利用牺牲层将杂质扩散到阻挡层，从而可以有效地提高阈值电压的调整精度，从而有助于提高器件的整体性能 。

公开(公告)号：US20150048458A1

公开(公告)日：2015-02-19

申请号：US14387305

申请日：2012-12-07

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huilong Zhu ,  Qiuxia Xu ,  Yanbo Zhang ,  Hong Yang

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/265 ,  H01L21/324

CPC classification number: H01L27/0922 ,  H01L21/265 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/324 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823864 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/7833

Abstract: Provided are a semiconductor device and a method for manufacturing the same. The method may include: forming source/drain regions in a semiconductor substrate; forming an interfacial oxide layer on the semiconductor substrate; forming a high K gate dielectric layer on the interfacial oxide layer; forming a first metal gate layer on the high K gate dielectric layer; implanting dopant to the first metal gate layer through conformal doping; and performing annealing to change an effective work function of a gate stack comprising the first metal gate layer, the high K gate dielectric layer, and the interfacial oxide layer.

Abstract translation: 提供半导体器件及其制造方法。 该方法可以包括：在半导体衬底中形成源/漏区; 在所述半导体衬底上形成界面氧化物层; 在界面氧化物层上形成高K栅介电层; 在所述高K栅极电介质层上形成第一金属栅极层; 通过共形掺杂将掺杂剂注入到第一金属栅极层; 以及执行退火以改变包括第一金属栅极层，高K栅介质层和界面氧化物层的栅极堆叠的有效功函数。

公开(公告)号：US09831089B2

公开(公告)日：2017-11-28

申请号：US14407210

申请日：2013-08-30

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Hong Yang ,  Wenwu Wang ,  Jiang Yan ,  Weichun Luo

IPC: H01L21/28 ,  H01L21/8238 ,  H01L21/321 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L21/28088 ,  H01L21/321 ,  H01L21/823842 ,  H01L29/517 ,  H01L29/66545

Abstract: A method for adjusting an effective work function of a metal gate. The method includes forming a metal gate arrangement comprising at least a metal work function layer, and performing plasma treatment on at least one layer in the metal gate arrangement. In this way, it is possible to adjust the effective work function of the metal gate in a relatively flexible way.

公开(公告)号：US20150008537A1

公开(公告)日：2015-01-08

申请号：US14494447

申请日：2014-09-23

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu ,  Qiuxia Xu ,  Yanbo Zhang ,  Hong Yang

IPC: H01L21/28 ,  H01L29/66 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L21/28105 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28185 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/66545

Abstract: An N-type MOSFET and a method for manufacturing the same are disclosed. In one aspect, the method comprises forming source/drain regions in a semiconductor substrate. The method also includes forming an interfacial oxide layer on the semiconductor substrate. The method also includes forming a high-k gate dielectric layer on the interfacial oxide layer. The method also includes forming a first metal gate layer on the high-k gate dielectric layer. The method also includes implanting dopants into the first metal gate layer through conformal doping. The method also includes annealing a gate stack to change an effective work function of the gate stack which includes the first metal gate layer, the high-k gate dielectric, and the interfacial oxide layer.

Abstract translation: 公开了一种N型MOSFET及其制造方法。 一方面，该方法包括在半导体衬底中形成源极/漏极区域。 该方法还包括在半导体衬底上形成界面氧化物层。 该方法还包括在界面氧化物层上形成高k栅介质层。 该方法还包括在高k栅极电介质层上形成第一金属栅极层。 该方法还包括通过共形掺杂将掺杂剂注入到第一金属栅极层中。 该方法还包括退火栅极堆叠以改变包括第一金属栅极层，高k栅极电介质和界面氧化物层的栅极堆叠的有效功函数。