公开(公告)号：US20150371934A1

公开(公告)日：2015-12-24

申请号：US14744946

申请日：2015-06-19

Applicant: J-DEVICES CORPORATION

Inventor： Hirokazu HONDA ,  Shinji WATANABE ,  Toshihiro IWASAKI ,  Kiminori ISHIDO ,  Koichiro NIWA ,  Takeshi MIYAKOSHI ,  Sumikazu HOSOYAMADA ,  Yoshikazu KUMAGAYA ,  Tomoshige CHIKAI ,  Shingo NAKAMURA ,  Shotaro SAKUMOTO ,  Hiroaki MATSUBARA

IPC: H01L23/495 ,  H01L21/48

CPC classification number: H01L23/3675 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/3677 ,  H01L23/4006 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/2518 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15151 ,  H01L2224/83

Abstract: A semiconductor package includes a support substrate arranged with a first aperture reaching a semiconductor device on a rear side, the semiconductor device is bonded via an adhesive to a surface of the support substrate, an insulating layer covering the semiconductor device, and wiring for connecting the semiconductor device and an external terminal through the insulating layer. The adhesive may form a part of the first aperture. In addition, a heat dissipation part may be arranged in the first aperture and a metal material may be filled in the first aperture.

Abstract translation: 一种半导体封装，包括布置有在后侧到达半导体器件的第一孔的支撑衬底，半导体器件通过粘合剂粘合到支撑衬底的表面，覆盖半导体器件的绝缘层和用于连接 半导体器件和通过绝缘层的外部端子。 粘合剂可以形成第一孔的一部分。 此外，可以在第一孔中布置散热部，并且可以在第一孔中填充金属材料。

公开(公告)号：US20150243576A1

公开(公告)日：2015-08-27

申请号：US14620854

申请日：2015-02-12

Applicant: J-DEVICES CORPORATION

Inventor： Takeshi MIYAKOSHI ,  Sumikazu HOSOYAMADA ,  Yoshikazu KUMAGAYA ,  Tomoshige CHIKAI ,  Shingo NAKAMURA ,  Hiroaki MATSUBARA

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495

CPC classification number: H01L23/3135 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/467 ,  H01L23/473 ,  H01L23/49524 ,  H01L23/49531 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/49568 ,  H01L24/00 ,  H01L24/17 ,  H01L24/36 ,  H01L24/37 ,  H01L24/40 ,  H01L2224/16245 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40225 ,  H01L2224/73204 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/1203 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/1304 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A semiconductor device includes a lead frame; a circuit board located on the lead frame; a power device that includes a switching element and is mounted on the circuit board via a bump located between the power device and the circuit board; and a heat releasing member connected to the power device. The circuit board may be a multi-layer wiring board. The circuit board may include a capacitor element, a resistor element, an inductor element, a diode element and a switching element.

Abstract translation: 半导体器件包括引线框架; 位于引线框架上的电路板; 功率器件，其包括开关元件，并且经由位于功率器件和电路板之间的凸块安装在电路板上; 以及与所述动力装置连接的散热构件。 电路板可以是多层布线板。 电路板可以包括电容器元件，电阻元件，电感器元件，二极管元件和开关元件。

公开(公告)号：US20140159215A1

公开(公告)日：2014-06-12

申请号：US14099288

申请日：2013-12-06

Applicant: J-DEVICES CORPORATION

Inventor： Yoshiyuki Tomonaga ,  Mitsuru Ooida ,  Katsumi Watanabe ,  Hidenari Sato

IPC: H01L23/495 ,  H01L21/56

CPC classification number: H01L23/49568 ,  H01L21/56 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/4334 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4813 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/10162 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A semiconductor device having a substrate including a plurality of external terminals on a rear surface and a plurality of bonding terminals electrically connected to the plurality of external terminals on a front surface, a semiconductor chip mounted on the front surface of the substrate, a surface of the chip including a plurality of bonding pads, a plurality of bonding wires connecting between the plurality of bonding pads or between the plurality of bonding terminals and the plurality of bonding wires respectively, a first sealing layer sealing the front surface of the substrate, the plurality of bonding wires and the semiconductor chip, and a second sealing layer comprised of the same material as the first sealing, the second sealing layer being formed above the first sealing layer.

Abstract translation: 一种半导体器件，具有在后表面上具有多个外部端子的基板和与前表面上的多个外部端子电连接的多个接合端子，安装在基板的前表面上的半导体芯片， 所述芯片包括多个接合焊盘，多个接合线，分别连接在所述多个接合焊盘之间或者在所述多个接合端子和所述多个接合线之间，密封所述衬底的前表面的第一密封层， 的接合线和半导体芯片，以及由与第一密封件相同的材料构成的第二密封层，第二密封层形成在第一密封层的上方。

公开(公告)号：US11488886B2

公开(公告)日：2022-11-01

申请号：US16592213

申请日：2019-10-03

Applicant: J-DEVICES CORPORATION

Inventor： Masao Hirobe

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/10 ,  H01L23/04 ,  H01L23/373

Abstract: There is provided a semiconductor device including a substrate whose surface is made of an insulation material, a semiconductor chip flip-chip connected on the substrate, and a heat sink bonded to the semiconductor chip via a thermal interface material and fixed to the substrate outside the semiconductor chip, in which the heat sink has a protrusion part protruding toward the substrate and bonded to the substrate via a conductive resin between a part bonded to semiconductor chip and a part fixed to the substrate and the heat sink has a stress absorbing part. According to the present invention, the protrusion part of the heat sink is prevented from being peeled off from the substrate at the part where the protrusion part of the heat sink is bonded to the substrate.

公开(公告)号：US10910294B2

公开(公告)日：2021-02-02

申请号：US16431691

申请日：2019-06-04

Applicant: J-Devices Corporation

Inventor： Kenji Nishikawa

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

Abstract: A packaged electronic device includes a substrate comprising a die pad and a lead spaced apart from the die. An electronic device is attached to the die pad top side. A conductive clip is connected to the substrate and the electronic device, and the conductive clip comprises a plate portion attached to the device top side with a conductive material, a clip connecting portion connected to the plate portion and the lead, and channels disposed to extend inward from a lower side of the plate portion above the device top side. The conductive material is disposed within the channels. In another example, the plate portion comprises a lower side having a first sloped profile in a first cross-sectional view such that an outer section of the first sloped profile towards a first edge portion of the plate portion is spaced away from the electronic device further than an inner section of the first sloped profile towards a central portion of the plate portion. Other examples and related methods are also disclosed herein.

公开(公告)号：US10559523B2

公开(公告)日：2020-02-11

申请号：US16053965

申请日：2018-08-03

Applicant: J-DEVICES CORPORATION

Inventor： Masafumi Suzuhara

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L23/00

Abstract: A semiconductor package includes a die pad; a plurality of external connection terminals located around the die pad; a semiconductor chip located on a top surface of the die pad and electrically connected with the plurality of external connection terminals; and a sealing member covering the die pad, the plurality of external connection terminals and the semiconductor chip and exposing an outer terminal of each of the plurality of external connection terminals. A side surface of the outer terminal of each of the plurality of external connection terminals includes a first area, and the first area is plated.

公开(公告)号：US10553456B2

公开(公告)日：2020-02-04

申请号：US15472387

申请日：2017-03-29

Applicant: J-DEVICES CORPORATION

Inventor： Yasuyuki Takehara ,  Kazuhiko Kitano

IPC: H01L21/56 ,  H01L23/29 ,  H01L23/14 ,  H01L23/13 ,  H01L21/48 ,  H01L23/31 ,  H01L23/00 ,  H01L21/768 ,  H01L23/544 ,  H01L23/492

Abstract: A semiconductor package includes a substrate having at least one recessed portion, a semiconductor device located on a surface of the substrate, the surface having the at least one recessed portion, and a resin insulating layer covering the semiconductor device.

公开(公告)号：US20180342443A1

公开(公告)日：2018-11-29

申请号：US16053965

申请日：2018-08-03

Applicant: J-DEVICES CORPORATION

Inventor： Masafumi Suzuhara

IPC: H01L23/495 ,  H01L21/48 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/49524 ,  H01L21/4825 ,  H01L21/4842 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3142 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49565 ,  H01L23/49582

Abstract: A semiconductor package includes a die pad; a plurality of external connection terminals located around the die pad; a semiconductor chip located on a top surface of the die pad and electrically connected with the plurality of external connection terminals; and a sealing member covering the die pad, the plurality of external connection terminals and the semiconductor chip and exposing an outer terminal of each of the plurality of external connection terminals. A side surface of the outer terminal of each of the plurality of external connection terminals includes a first area, and the first area is plated.

公开(公告)号：US10062638B2

公开(公告)日：2018-08-28

申请号：US15446426

申请日：2017-03-01

Applicant: J-DEVICES CORPORATION

Inventor： Masafumi Suzuhara

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49524 ,  H01L21/4825 ,  H01L21/4842 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3142 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49565 ,  H01L23/49582

Abstract: A semiconductor package includes a die pad; a plurality of external connection terminals located around the die pad; a semiconductor chip located on a top surface of the die pad and electrically connected with the plurality of external connection terminals; and a sealing member covering the die pad, the plurality of external connection terminals and the semiconductor chip and exposing an outer terminal of each of the plurality of external connection terminals. A side surface of the outer terminal of each of the plurality of external connection terminals includes a first area, and the first area is plated.

公开(公告)号：US09837382B2

公开(公告)日：2017-12-05

申请号：US15089630

申请日：2016-04-04

Applicant: J-DEVICES CORPORATION

Inventor： Shinji Watanabe ,  Toshihiro Iwasaki ,  Michiaki Tamakawa

IPC: H01L23/373 ,  H01L25/065 ,  H01L25/00 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L21/60 ,  H01L23/31 ,  H01L23/36 ,  H01L23/498

CPC classification number: H01L25/0655 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/36 ,  H01L23/49844 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L25/50 ,  H01L2021/60022 ,  H01L2224/04105 ,  H01L2224/16245 ,  H01L2224/2518 ,  H01L2224/73259 ,  H01L2224/81005 ,  H01L2224/82005 ,  H01L2224/92224 ,  H01L2924/18162

Abstract: Thermal resistance is reduced from an element surface of a semiconductor chip to the rear surface of a semiconductor package. Split patterning of a metal is easily carried out, stress produced by a thermal expansion coefficient between silicon and metal is significantly reduced and environment reliability is improved. Low cost is realized by manufacturing a semiconductor package without using a TIM material. A semiconductor package is provided including a semiconductor chip including a first surface and a second surface opposed to the first surface and covered with a resin, an electrode being arranged over the first surface, a first wiring connected to the first surface directly or via a first opening arranged in the resin, and a second wiring connected to the second surface via a second opening arranged in the resin.