公开(公告)号：WO2008030751A3

公开(公告)日：2008-05-08

申请号：PCT/US2007077200

申请日：2007-08-30

Applicant: MICROCHIP TECH INC ,  GULSEN JOHN K ,  BOWLING STEPHEN

Inventor： GULSEN JOHN K ,  BOWLING STEPHEN

IPC: H05B41/392

CPC classification number: H05B41/3921

Abstract: Pulse Density Modulation (PDM) is used to control the amount of light from a fluorescent lamp by applying a voltage to the lamp filaments at a low frequency that is approximately at a series resonant frequency of the lamp ballast inductor and the lamp filament capacitor, no voltage and a voltage at a high frequency. The lamp gas ionizes to produce light only when the low frequency voltage is applied. The fluorescent lamp gas does not ionize when the voltage at the high frequency is applied, but the high frequency voltage keeps the lamp filaments warm during low light output conditions. The low frequency, no and high frequency voltages have time periods that occur within a modulation frame time period that repeats continuously. The ratio of the low frequency voltage time period, and the no voltage and/or high frequency voltage time periods determine the light output of the fluorescent lamp.

Abstract translation: 脉冲密度调制（PDM）用于通过以近似于灯镇流器电感器和灯丝电容器的串联谐振频率的低频率向灯丝施加电压来控制来自荧光灯的光量，no 电压和高频电压。 只有当施加低频电压时，灯气才电离以产生光。 荧光灯气体在施加高频电压时不会电离，但高频电压在低光输出条件下保持灯丝温度。 低频率，无频率和高频率电压具有在连续重复的调制帧时间段内发生的时间段。 低频电压时间段与无电压和/或高频电压时间段的比率决定了荧光灯的光输出。

公开(公告)号：WO2008014244A2

公开(公告)日：2008-01-31

申请号：PCT/US2007074194

申请日：2007-07-24

Applicant: MICROCHIP TECH INC ,  SMIT MARIA ,  DAWSON STEVEN ,  BOLES BRIAN

Inventor： DAWSON STEVEN ,  BOLES BRIAN ,  SMIT WILLEM

CPC classification number: G06F13/28

Abstract: A method of performing a direct memory access has the steps of selecting a peripheral device for performing a direct memory access through a direct memory access controller; providing a partial address by the peripheral device to the direct memory access controller; and forming the source or destination address by combining the partial address with selected bits from a source register within the direct memory access controller.

Abstract translation: 执行直接存储器访问的方法具有选择用于通过直接存储器访问控制器执行直接存储器访问的外围设备的步骤; 通过所述外围设备向所述直接存储器访问控制器提供部分地址; 以及通过将部分地址与来自直接存储器访问控制器内的源寄存器的选定位组合来形成源或目的地地址。

公开(公告)号：WO2008011408A2

公开(公告)日：2008-01-24

申请号：PCT/US2007073683

申请日：2007-07-17

Applicant: MICROCHIP TECH INC ,  ROGERS J CLARK ,  KRIS BRYAN

Inventor： ROGERS J CLARK ,  KRIS BRYAN

IPC: H01L23/50

CPC classification number: G06F13/4072 ,  G06F13/4022

Abstract: An integrated circuit device having at least one bond pad is coupled to a selectable plurality of input-output functionalities, e.g., an oscillator input, an analog input, an analog output, a digital input and a digital output. These analog, digital and oscillator functionalities may selectably share the same integrated circuit package external connection.

Abstract translation: 具有至少一个键合焊盘的集成电路器件耦合到可选的多个输入 - 输出功能，例如振荡器输入，模拟输入，模拟输出，数字输入和数字输出。 这些模拟，数字和振荡器功能可以有选择地共享相同的集成电路封装外部连接。

公开(公告)号：WO2007050663A2

公开(公告)日：2007-05-03

申请号：PCT/US2006041585

申请日：2006-10-25

Applicant: MICROCHIP TECH INC ,  KUPPUSAMY VANITHA ,  ROGERS CLARK

Inventor： KUPPUSAMY VANITHA ,  ROGERS CLARK

IPC: H03B1/00

CPC classification number: H03M1/0872 ,  H03B2200/0034 ,  H03B2200/0048 ,  H03B2201/0283 ,  H03L1/00 ,  H03M1/742

Abstract: Current sources are selectively coupled to a current controlled frequency determining circuit of an oscillator. A buffer amplifier has an input coupled to the current controlled frequency determining circuit of the oscillator and the buffer amplifier output is selectively coupled to the current sources not coupled to the frequency determining circuit of the oscillator. The buffer amplifier output maintains substantially the voltage of the current controlled frequency determining circuit on each of the current sources not coupled to the frequency determining circuit so that when any current source is coupled thereto, there is substantially no voltage difference therebetween. This substantially prevents generation of undesirable frequency spikes during coupling of the current sources to the frequency determining circuit of the oscillator.

Abstract translation: 电流源选择性地耦合到振荡器的电流控制频率确定电路。 缓冲放大器具有耦合到振荡器的电流控制频率确定电路的输入，并且缓冲放大器输出选择性地耦合到未耦合到振荡器的频率确定电路的电流源。 缓冲放大器输出基本上维持不耦合到频率确定电路的每个电流源上的电流控制频率确定电路的电压，使得当任何电流源耦合到其上时，它们之间基本上没有电压差。 这实质上防止了在将电流源耦合到振荡器的频率确定电路期间产生不期望的频率尖峰。

公开(公告)号：WO2005104006A3

公开(公告)日：2006-03-30

申请号：PCT/US2005012934

申请日：2005-04-14

Applicant: MICROCHIP TECH INC ,  NOLAN JAMES B ,  LEE THOMAS YOUBOK ,  LAMPHIER ALAN ,  LOURENS RUAN ,  VERNIER STEVE

Inventor： NOLAN JAMES B ,  LEE THOMAS YOUBOK ,  LAMPHIER ALAN ,  LOURENS RUAN ,  VERNIER STEVE

IPC: G06K7/00 ,  G06K19/07 ,  G07C9/00 ,  H04Q5/22

CPC classification number: G06K19/0705 ,  G06K19/0723 ,  G07C9/00309 ,  G07C2009/0038

Abstract: A bidirectional remote keyless entry (RKE) transponder comprises an analog front-end (AFE) having a programmable wake-up filter that predefines the waveform timing of the desired input signal, minimum modulation depth requirement of input signal, and independently controllable channel gain reduction of each of its three channels, X, Y, and Z. The wake-up filter parameters are the length of high and low durations of wake-up pulses that may be programmed in a configuration register. The wake-up filter allows the AFE to output demodulated data if the input signal meets its wake-up filter requirement, but does not output the demodulated data otherwise. The AFE output pin is typically connected to an eternal device for control, such as a microcontroller (MCU). The external device typically stays in low current sleep (or standby) mode when the AFE has no output and switches to high current wake-up (or active) mode when the AFE has output. Therefore, in order to keep the eternal control device in the low current sleep mode when there is no desired input signal, it is necessary to keep no output at the AFE output pin. This can be achieved by controlling the wake-up filter parameters, minimum modulation depth requirement of input signal, and. channel gains of the AFE device. These features can reduce false-wake up of the bidirectional RKE transponder due to undesired input signals such as noise signals.

Abstract translation: 双向远程无钥匙进入（RKE）转发器包括具有可编程唤醒滤波器的模拟前端（AFE），其预定义所需输入信号的波形定时，输入信号的最小调制深度要求以及独立可控的信道增益减小 的三个通道中的每一个，X，Y和Z.唤醒滤波器参数是可以在配置寄存器中编程的唤醒脉冲的高和低持续时间的长度。 唤醒滤波器允许AFE在输入信号满足唤醒滤波器要求时输出解调数据，否则不输出解调数据。 AFE输出引脚通常连接到用于控制的永久性设备，例如微控制器（MCU）。 当AFE没有输出时，外部设备通常保持在低电流休眠（或待机）模式，并且当AFE输出时，外部设备切换到高电流唤醒（或有效）模式。 因此，为了在不需要输入信号的情况下将永久控制装置保持在低电流睡眠模式，需要在AFE输出引脚处不输出。 这可以通过控制唤醒滤波器参数，输入信号的最小调制深度要求来实现。 AFE设备的通道增益。 这些功能可以减少由于不期望的输入信号（如噪声信号）引起的双向RKE转发器的假唤醒。

公开(公告)号：WO2006023427A2

公开(公告)日：2006-03-02

申请号：PCT/US2005028912

申请日：2005-08-12

Applicant: MICROCHIP TECH INC ,  KRIS BRYAN

Inventor： KRIS BRYAN

IPC: H03K7/08

CPC classification number: H03K7/08

Abstract: A pulse width modulation (PWM) generator featuring very high speed and high resolution capability and the ability to generate standard complementary PWM, push-pull PWM, variable offset PWM, multiphase PWM, current limit PWM, current reset PWM, and independent time base PWM while further providing automatic triggering for an analog-to­digital conversion (ADC) module that is precisely timed relative to the PWM signals. Applications include control of a switching power supply that requires very high speed operation to obtain high resolution at high switching frequencies, and the ability to vary the phase relationships among the PWM output signals driving the power supply power components. A single PWM duty cycle register may be used for updating any and/or all PWM generators at once to reduce the workload of a digital processor as compared to updating multiple duty cycle registers.

Abstract translation: 具有极高速度和高分辨率能力的脉宽调制（PWM）发生器，能够产生标准互补PWM，推挽PWM，可变偏移PWM，多相PWM，限流PWM，电流复位PWM和独立时基PWM 同时进一步提供相对于PWM信号精确定时的模数转换（ADC）模块的自动触发。 应用包括控制开关电源，其需要非常高的速度操作以在高开关频率下获得高分辨率，以及改变驱动电源功率部件的PWM输出信号之间的相位关系的能力。 与更新多个占空比寄存器相比，可以使用单个PWM占空比寄存器来一次更新任何和/或所有PWM发生器，以减少数字处理器的工作负载。

公开(公告)号：WO2005119466A3

公开(公告)日：2006-03-02

申请号：PCT/US2005018516

申请日：2005-05-26

Applicant: MICROCHIP TECH INC ,  JULICHER JOSEPH HARRY ,  MASGRAS CRISTIAN P ,  PYSKA MICHAEL

Inventor： JULICHER JOSEPH HARRY ,  MASGRAS CRISTIAN P ,  PYSKA MICHAEL

IPC: G06F13/38 ,  H04Q11/00

CPC classification number: G06F13/385

Abstract: A digital device comprising a digital processor, a streaming input-output (I/O) port module, and an interface port module having an independent data and control bus may be independently coupled to the streaming I/O port module. The streaming I/O port module may also be coupled to the digital processor, wherein the digital process may control whether the streaming I/O port module is coupled to either the interface port module or the digital processor. The interface port module may also be coupled to the digital processor independently of the streaming I/O port module. The interface port module and the streaming I/O port module may be adapted for parallel and/or serial data transfers. The streaming I/O port may be used to couple an external peripheral device to either the digital processor or to the interface port module.

Abstract translation: 包括数字处理器，流输入输出（I / O）端口模块和具有独立数据和控制总线的接口端口模块的数字设备可以独立地耦合到流I / O端口模块。 流式I / O端口模块还可以耦合到数字处理器，其中数字处理可以控制流I / O端口模块是否耦合到接口端口模块或数字处理器。 接口端口模块也可以独立于流I / O端口模块耦合到数字处理器。 接口端口模块和流I / O端口模块可适用于并行和/或串行数据传输。 流式I / O端口可用于将外部外围设备耦合到数字处理器或接口端口模块。

公开(公告)号：WO02073796A2

公开(公告)日：2002-09-19

申请号：PCT/US0207118

申请日：2002-03-11

Applicant: MICROCHIP TECH INC

Inventor： BRUNOLLI MICHAEL ,  HOANG CHINH ,  KATZ PAUL N

IPC: H03M1/76 ,  H03M1/66 ,  H03M1/68 ,  H03G

CPC classification number: H03M1/682 ,  H03M1/765

Abstract: A digitally switched impedance has improved linearity by minimizing the amount of impedance error introduced by switches used to switch the impedance elements comprising the digitally switched impedance. Improved settling time of the digitally switched impedance is achieved by reducing the amount of switch capacitance connected to the output of the digitally switched impedance. The digitally switched impedance may be fabricated on an integrated circuit die and the switches may be fabricated with complementary metal oxide semiconductor (CMOS) transistors. The number of impedances needed for a desired number of impedance step changes is reduced by using two major impedance ranks and one minor impedance rank, or two minor impedance ranks and one major impedance rank connected in series.

Abstract translation: 通过最小化由用于切换包括数字切换阻抗的阻抗元件的开关引起的阻抗误差的量，数字开关阻抗具有改善的线性度。 通过减少连接到数字开关阻抗的输出的开关电容量，可以实现数字开关阻抗的改善建立时间。 数字开关阻抗可以制造在集成电路管芯上，并且开关可以用互补金属氧化物半导体（CMOS）晶体管制造。 通过使用两个主要阻抗等级和一个次要阻抗等级，或两个次要阻抗等级和一个主要阻抗等级串联连接，减少所需数量的阻抗阶跃变化所需的阻抗数量。

公开(公告)号：WO0031779A9

公开(公告)日：2002-08-29

申请号：PCT/US9927885

申请日：1999-11-24

Applicant: MICROCHIP TECH INC

Inventor： ALEXANDER SAM E ,  YACH RANDY L ,  ST AMAND ROGER

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/822 ,  H01L27/04 ,  H01L27/08

CPC classification number: H01L28/40 ,  H01L27/0805

Abstract: An improved high quality factor capacitive device is implemented on a single, monolithic integrated circuit. The new layout techniques improve the quality factor (Q) of the capacitor by reducing intrinsic resistance of the capacitor by means of reducing the distance between the metal contacts of the top and bottom conductive plates. The layout techniques require laying out the top conductive plate of the capacitor in strips such that metal contacts from the bottom conductive plate pass in between the strips and through the dielectric layer. Alternatively, the apertures may be etched into the top conductive plate so that metal contacts pass through the apertures and connect to the bottom conductive plate.

Abstract translation: 改进的高品质因素电容器件在单个单片集成电路上实现。 新的布局技术通过减小顶部和底部导电板的金属触点之间的距离来降低电容器的固有电阻，从而提高了电容器的品质因数（Q）。 布局技术需要将带状电容器的顶部导电板布置成使得来自底部导电板的金属接触通过条带之间并通过介电层。 或者，孔可以被蚀刻到顶部导电板中，使得金属触点穿过孔并连接到底部导电板。

公开(公告)号：WO0024127A9

公开(公告)日：2001-12-13

申请号：PCT/US9924569

申请日：1999-10-20

Applicant: MICROCHIP TECH INC

Inventor： BARNA PAUL

IPC: H03K19/0175

CPC classification number: H03K19/017509

Abstract: A variable low voltage signal translator uses a driver (12) for outputting a low voltage signal translation. A control circuit (18) is coupled to the driver (12) for enabling and disabling the driver (12) wherein the control circuit (18) has an input coupled to the signal to be translated. One terminal of the pull-up resistor (14) is coupled to an output of the driver (12). A second terminal of the pull-up resistor (14) is coupled to a voltage supply (16) which provides the low voltage level of the variable low voltage signal translator.

Abstract translation: 可变低电压信号转换器使用驱动器（12）来输出低电压信号转换。 控制电路（18）耦合到驱动器（12），用于启用和禁用驱动器（12），其中控制电路（18）具有耦合到要被转换的信号的输入。 上拉电阻器（14）的一个端子耦合到驱动器（12）的输出端。 上拉电阻器（14）的第二端子耦合到提供可变低电压信号转换器的低电压电平的电压源（16）。