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    A low power flip flop circuit
    82.
    发明公开
    A low power flip flop circuit 有权
    低功耗触发器电路

    公开(公告)号：EP1940027A3

    公开(公告)日：2010-04-14

    申请号：EP07150459.1

    申请日：2007-12-28

    Applicant: STMicroelectronics Pvt. Ltd

    Inventor： Jain, Abhishek

    IPC: H03K19/00 ,  H03K3/287

    CPC classification number: H03K19/0013 ,  H03K3/012 ,  H03K3/356156

    Abstract: The present invention provides a flip flop circuit (300) utilizing low power dissipation. The low power flip-flop circuit includes a flip-flop circuit (302), a clock generating circuit(306), and a sensing circuit (304). The flip flop is positive edge triggered and operates on an internally generated pseudo clock signal (CP). The sensing circuit senses a change in an input signal and an output signal of the flip-flop output. The clock generating circuit generates a pseudo clock signal (CP) with a sharp rise and fall depending on an external clock signal. In very large scale integration (VLSI) applications the data activity is generally of the order of 2-10 % of clock activity, so, the switching current which flows between a power supply to a ground terminal, when the data is constant and clock is toggling leads to high power dissipation and electromagnetic emissions (which has now become a serious problem in VLSI digital designs).

    System and method for multiple-phase clock generation
    84.
    发明公开
    System and method for multiple-phase clock generation 审中-公开
    系统和方法，用于产生多相位时钟

    公开(公告)号：EP1811664A3

    公开(公告)日：2010-01-27

    申请号：EP06127217.5

    申请日：2006-12-27

    Applicant: STMicroelectronics Pvt. Ltd.

    Inventor： Sen, Tanmoy ,  Kumar, Anand ,  Kumar Jain, Deependra Padam Chand Jain

    IPC: H03K5/15

    CPC classification number: H03K3/0315 ,  H03K3/03 ,  H03K5/15013 ,  H03K5/15026 ,  H03K5/1506 ,  H03K2005/00241 ,  H03K2005/00247 ,  H03L7/095 ,  H03L7/0995 ,  Y10S331/02

    Abstract: A system and method for multiple phase clock generation is disclosed. The disclosed multiple phase clock circuit comprises of a multiple stage voltage controlled oscillator (401) (VCO) and multiple clock dividers (402A-402M). The voltage controlled oscillator (VCO) is made to operate at frequency 'N' times higher than the required output frequency. It generates 'M' equally spaced outputs having different phases but same frequency which are sent to multiple clock dividers. A modified Johnson counter is used as a clock divider. Each counter divides the frequency of the clock signal by N. As a result, each of the M outputs of the VCO are divided into N outputs, thereby making a total of 'M x N' equally spaced outputs. These output clock pulses have same frequency but different phases. A sequential logic (403) is provided within the device for enabling the Johnson counters as soon as the VCO starts giving output. This maintains the sequence of the output of the Johnson counters.

    Memory architecture for image processing
    85.
    发明公开
    Memory architecture for image processing 审中-公开
    存储器体系结构的图像处理

    公开(公告)号：EP1804214A3

    公开(公告)日：2009-10-21

    申请号：EP06027049.3

    申请日：2006-12-29

    Applicant: STMicroelectronics Pvt. Ltd.

    Inventor： Mahesh, Chandra

    IPC: G06T1/60 ,  G06T3/60

    CPC classification number: G06T1/60

    Abstract: The present invention relates to a memory architecture (10) for image processing comprising a memory array having multiple multi-byte memory data paths of equal multi-byte data width, and a multiplexing structure (13) connected to the output of the multiple multi-byte data paths, capable of selectively providing a multi-byte data path of a desired width containing a desired permutation of bytes chosen from one or more of the multiple data paths.

    An apparatus and method for entering and exiting low power mode
    86.
    发明公开
    An apparatus and method for entering and exiting low power mode 有权
    对于进入和退出低功率模式的方法和装置

    公开(公告)号：EP1653331A3

    公开(公告)日：2009-09-16

    申请号：EP05110131.9

    申请日：2005-10-28

    Applicant: STMicroelectronics Pvt. Ltd

    Inventor： DHIMAN, Gaurav ,  KAPOOR, Gaurav

    IPC: G06F9/445 ,  G06F1/32

    CPC classification number: G06F1/30 ,  G06F1/3203 ,  G06F9/4418

    Abstract: An apparatus for entering and exiting low power mode comprising a processor having a cache; a power management mechanism connected to said processor for controlling a plurality of power management states, at least one of said power management states being a low latency low power state; a memory subsystem including a self sustaining mechanism connected to said processor for retaining data during said low power state; a prefetching means in said memory subsystem for loading instructions into a cache prior to entering said low power state; a disabling mechanism in said processor for disabling any interrupts that may disturb said prefetched instructions; an enabling means in said memory subsystem for initiating the self sustaining operation of said memory subsystem; a detecting means connected to said processor for sensing a trigger to exit from said low power state; and a restoring means in said power management mechanism for restoring the clock of said apparatus; thereby said processor disabling said self sustaining operation and resuming normal operation at the end of said low power state.

    A low power flip flop circuit
    88.
    发明公开
    A low power flip flop circuit 有权
    Schwachstrom触发器-Schaltung

    公开(公告)号：EP1940027A2

    公开(公告)日：2008-07-02

    申请号：EP07150459.1

    申请日：2007-12-28

    Applicant: STMicroelectronics Pvt. Ltd

    Inventor： Jain, Abhishek

    IPC: H03K19/00 ,  H03K3/287

    CPC classification number: H03K19/0013 ,  H03K3/012 ,  H03K3/356156

    Abstract: The present invention provides a flip flop circuit (300) utilizing low power dissipation. The low power flip-flop circuit includes a flip-flop circuit (302), a clock generating circuit(306), and a sensing circuit (304). The flip flop is positive edge triggered and operates on an internally generated pseudo clock signal (CP). The sensing circuit senses a change in an input signal and an output signal of the flip-flop output. The clock generating circuit generates a pseudo clock signal (CP) with a sharp rise and fall depending on an external clock signal. In very large scale integration (VLSI) applications the data activity is generally of the order of 2-10 % of clock activity, so, the switching current which flows between a power supply to a ground terminal, when the data is constant and clock is toggling leads to high power dissipation and electromagnetic emissions (which has now become a serious problem in VLSI digital designs).

    Abstract translation: 本发明提供一种利用低功耗的触发电路（300）。 低功率触发电路包括触发电路（302），时钟发生电路（306）和感测电路（304）。 触发器为正边沿触发，并在内部产生的伪时钟信号（CP）上工作。 感测电路检测输入信号和触发器输出的输出信号的变化。 时钟发生电路根据外部时钟信号产生急剧上升和下降的伪时钟信号（CP）。 在超大规模集成（VLSI）应用中，数据活动通常是时钟活动的2-10％的量级，所以当数据为恒定的时候，在接地端子的电源之间流动的开关电流， 切换导致高功率耗散和电磁辐射（现在已成为VLSI数字设计中的严重问题）。

    A low dropout regulator (LDO)
    89.
    发明公开
    A low dropout regulator (LDO) 有权
    稳压器，具有低压降电压

    公开(公告)号：EP1806640A3

    公开(公告)日：2008-05-07

    申请号：EP06126405.7

    申请日：2006-12-18

    Applicant: STMicroelectronics Pvt. Ltd.

    Inventor： Mandal, Sajal Kumar

    IPC: G05F1/565

    CPC classification number: G05F1/575

    Abstract: The present invention provides a low dropout (LDO) regulator with a stability compensation circuit. A "zero frequency" tracking as well as "non-dominant parasitic poles' frequency reshaping" are performed to achieve a good phase margin for the LDO by means of the compensation circuit. In this compensation method neither a large load capacitor nor its equivalent series resistance (ESR) is needed to stabilize a regulator. LDO regulators, in system on chip (SoC) application, having load capacitors in the range of few nano-Farads to few hundreds of nano-Farads can be efficiently compensated with this compensation method. A dominant pole for the regulator is realized at an internal node and the second pole at an output node of the regulator is tracked with a variable capacitor generated zero over a range of load current to cancel the effect of each other. A third pole of the system is pushed out above the unity gain frequency of the open loop transfer function with the help of the frequency compensation circuit. The compensation technique is very effective in realizing a low power, low-load-capacitor LDO desirable for system on chip applications.

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