公开(公告)号：KR1020040078273A

公开(公告)日：2004-09-10

申请号：KR1020030013124

申请日：2003-03-03

Applicant: 삼성전자주식회사

Inventor： 김강영 ,  조욱래 ,  강태경

IPC: H01L27/11

Abstract: PURPOSE: An SRAM device having a strapping region is provided to reduce the off-current of driving transistors and the power consumption by increasing the threshold voltages of the driving transistors. CONSTITUTION: A plurality of cell active regions(101) are formed with the first active region formed on the first well region and the second active region formed on the second well region. An extended part of the second well region is arranged on a strapping region(70). The first and the second gate electrodes(110a,110b) are formed across the first and the second active regions. The first and the second gate electrodes are formed in parallel to each other. A common source region is extended from the second active region between the first and the second gate electrodes. A common source line(120) is electrically connected to the common source region. The common source line is formed across the strapping region. The first ground voltage supply line(130) is formed across the common source line within the strapping region and is electrically connected to the common source line. A well voltage supply line is arranged in one side of the ground line within the strapping region and is electrically connected to the extended part of the second well.

Abstract translation: 目的：提供具有带状区域的SRAM器件，以通过增加驱动晶体管的阈值电压来减小驱动晶体管的截止电流和功耗。 构成：多个单元有源区（101）形成有形成在第一阱区上的第一有源区和形成在第二阱区上的第二有源区。 第二阱区域的延伸部分布置在捆扎区域（70）上。 第一和第二栅极电极（110a，110b）横跨第一和第二有源区域形成。 第一和第二栅电极彼此平行地形成。 公共源极区域从第一和第二栅电极之间的第二有源区延伸。 公共源极线（120）电连接到公共源极区域。 公共源极线跨越捆扎区域形成。 第一接地电压供应线（130）跨越捆扎区域内的公共源极线形成，并且与公共源极线电连接。 阱电压供给线布置在捆扎区域内的接地线的一侧，并且电连接到第二阱的延伸部分。

公开(公告)号：KR1020040067602A

公开(公告)日：2004-07-30

申请号：KR1020030004807

申请日：2003-01-24

Applicant: 삼성전자주식회사

Inventor： 이종철 ,  조욱래 ,  김수철

IPC: G11C11/40

CPC classification number: G11C29/1201 ,  G11C29/48 ,  G11C2029/1804

Abstract: PURPOSE: A semiconductor memory device tested by an SDR(Single Data Rate) mode and a DDR(Double Data Rate) mode at a merged DQ mode test process is provided to test the semiconductor memory device by using the SDR mode and the DDR mode at the merged DQ mode test process. CONSTITUTION: A semiconductor memory device tested by an SDR mode and a DDR mode at a merged DQ mode test process includes a first path part, a second path part, and an integrated output signal generator. The first path part(310) is used for transferring selectively the first inner data, which are outputted, from the first edge block of clock signals. The second path part(330) is used for transferring selectively the second inner data, which are outputted, from the second edge block of the clock signals. The integrated output signal generator(350) is used for outputting integrated output signals of an SDR mode or a DDR mode in response to the outputs of the first and the second path parts.

Abstract translation: 目的：提供在合并DQ模式测试过程中通过SDR（单数据速率）模式和DDR（双倍数据速率）模式测试的半导体存储器件，以通过使用SDR模式和DDR模式来测试半导体存储器件 合并的DQ模式测试过程。 构成：在合并DQ模式测试过程中通过SDR模式和DDR模式测试的半导体存储器件包括第一路径部分，第二路径部分和集成输出信号发生器。 第一路径部分（310）用于选择性地传送从时钟信号的第一边缘块输出的第一内部数据。 第二路径部分（330）用于选择性地传送从时钟信号的第二边缘块输出的第二内部数据。 集成输出信号发生器（350）用于响应于第一和第二路径部分的输出而输出SDR模式或DDR模式的集成输出信号。

公开(公告)号：KR100426989B1

公开(公告)日：2004-04-13

申请号：KR1020010033086

申请日：2001-06-13

Applicant: 삼성전자주식회사

Inventor： 박용대 ,  조욱래

IPC: H01L23/544

CPC classification number: H01L23/5382 ,  G01R31/2884 ,  H01L23/50 ,  H01L24/48 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: 생산성 향상을 위해 집적회로 칩을 패키징한 상태에서 상기 집적회로 칩내의 옵션 패드에 제어신호를 인가하는 방법이 개시된다. 그러한 방법은, 상기 집적회로 칩을 패키징한 집적회로 패키지에 할당된 복수의 전원인가용 핀들중 적어도 하나의 핀을, 상기 집적회로 칩내에 설치된 전원 패드에는 연결함이 없이 상기 옵션 패드에 독립적으로 연결하여 두고, 상기 옵션 패드와 연결된 상기 전원인가용 핀을 통해 외부에서 제어신호를 인가하는 것을 특징으로 한다.

Abstract translation: 公开了一种用于在其封装级将控制信号传输到集成电路芯片的选择焊盘的方法和设备。 该方法包括以下步骤：电隔离集成电路封装的多个共同连接的功率发送引脚中的一个; 将电隔离的电力传输管脚连接到选择焊盘，从而通过电隔离的电力传输管脚将来自外部的控制信号传输到选择焊盘。

公开(公告)号：KR1020040000918A

公开(公告)日：2004-01-07

申请号：KR1020020035932

申请日：2002-06-26

Applicant: 삼성전자주식회사

Inventor： 조욱래 ,  안기식 ,  이인열

IPC: G11C29/00

Abstract: PURPOSE: A memory device having a write driver to screen defect of a SRAM cell is provided to reduce test time and to screen a defective cell. CONSTITUTION: A SRAM cell is connected to a bit line and a complementary bit line. And a write driver(300) writes data to the bit line and the complementary bit line of the memory cell with the first and the second level in response to a write signal and a weak write signal. The write driver comprises the first and the second decoding part responding to the write signal and the data and the inverted data, and the first and the second load part(310,320) providing the first and the second level in response to the weak write signal, and the first and the second driver part(214,224) transferring the first and the second level to the bit line and the complementary bit line of the memory cell in response to the output of the first and the second decoding part respectively.

Abstract translation: 目的：提供具有用于屏蔽SRAM单元的缺陷的写入驱动器的存储器件，以减少测试时间并筛选有缺陷的单元。 构成：SRAM单元连接到位线和互补位线。 并且写入驱动器（300）响应于写入信号和弱写入信号，将数据写入具有第一和第二电平的存储器单元的位线和互补位线。 写驱动器包括响应于写信号和数据和反相数据的第一和第二解码部分，以及响应于弱写信号而提供第一和第二电平的第一和第二负载部分（310,320） 以及第一和第二驱动器部分（214,224）分别响应于第一和第二解码部分的输出而将第一和第二电平传送到存储器单元的位线和互补位线。

公开(公告)号：KR100410555B1

公开(公告)日：2003-12-18

申请号：KR1020010043049

申请日：2001-07-18

Applicant: 삼성전자주식회사

Inventor： 박정우 ,  조욱래 ,  김남석

IPC: G11C8/00

CPC classification number: H03L7/0805 ,  H03L7/07 ,  H03L7/0812

Abstract: An internal clock generating circuit and method for generating an internal clock phase-synchronized to an input clock with minimum delay and at high speed is disclosed. An internal clock generating circuit comprises a first delay control circuit for generating a first clock having the time delay of up to T/2 (where T is a cycle of an input clock) from the input clock and for generating a first variable delay control signal; and a second delay control circuit for generating a second clock in response to the first variable delay control signal, the second clock having the time delay of greater than T/2 from the input clock at an initial state and having the time delay of about T from the input clock in a phase-locked state.

Abstract translation: 公开了一种内部时钟产生电路和方法，用于产生与输入时钟以最小延迟和高速相位同步的内部时钟。 内部时钟产生电路包括第一延迟控制电路，用于从输入时钟产生具有高达T / 2（其中T是输入时钟的周期）的时间延迟的第一时钟并且用于产生第一可变延迟控制信号 ; 以及第二延迟控制电路，用于响应于第一可变延迟控制信号产生第二时钟，第二时钟从初始状态的输入时钟具有大于T / 2的时间延迟，并具有约T的时间延迟 从输入时钟处于锁相状态。

公开(公告)号：KR1020030091283A

公开(公告)日：2003-12-03

申请号：KR1020020029200

申请日：2002-05-27

Applicant: 삼성전자주식회사

Inventor： 손영재 ,  조욱래 ,  이광진

IPC: G11C29/00

CPC classification number: G11C29/12005 ,  G11C11/41 ,  G11C29/50 ,  G11C2029/5002 ,  G11C2029/5006

Abstract: PURPOSE: A circuit for screening the failure cells of a semiconductor memory device, a method for screening the same and a method for arranging the screen are provided to remove the time required for the stabilization after the voltage is changed so as to supply the power dropped at a predetermined voltage at a conventional tester. CONSTITUTION: A circuit for screening the failure cells of a semiconductor memory device includes a power voltage, a memory cell(400), a first driver(430) and a second driver(440). The first driver(430) is formed between the power voltage and the memory cell(400) for supplying the power voltage to the memory cell in response to the cell power control signal. And, the second driver(440) formed between the power voltage and the memory cell for supplying the voltage dropped by the predetermined voltage at the power voltage to the memory cell(400) in response to the cell power down signal.

Abstract translation: 目的：提供一种用于屏蔽半导体存储器件的故障单元的电路，其屏蔽方法和布置屏幕的方法，以消除在电压变化之后稳定所需的时间，从而提供掉电 在常规测试器处以预定电压。 构成：用于屏蔽半导体存储器件的故障单元的电路包括电源电压，存储单元（400），第一驱动器（430）和第二驱动器（440）。 第一驱动器（430）形成在电源电压和存储单元（400）之间，用于响应于单元功率控制信号向存储单元提供电源电压。 并且，形成在电源电压和存储单元之间的第二驱动器（440），用于响应于单元停电信号，将以电源电压下降的预定电压的电压提供给存储单元（400）。

公开(公告)号：KR1020030030218A

公开(公告)日：2003-04-18

申请号：KR1020010062065

申请日：2001-10-09

Applicant: 삼성전자주식회사

Inventor： 김남석 ,  조욱래 ,  이광진

IPC: H03K19/0175

CPC classification number: H03K3/356113 ,  H03K3/356165 ,  H03K5/06

Abstract: PURPOSE: A level converter is provided to be capable of minimizing performance lowering of a semiconductor chip and of increasing a level conversion speed. CONSTITUTION: A level converting part(110) outputs a level conversion signal(OUT) having a different level from a level of an input signal in response to a rising edge of the input signal(IN). A delay part(120) delays the level conversion signal(OUT) of the level converting part(110). A self reset part(130) generates a reset signal in response to the delayed level conversion signal. A pulse width of the level conversion signal(OUT) is established by a sum of the established delay and an internal operation delay, based on the reset signal.

Abstract translation: 目的：提供一种电平转换器，以使半导体芯片的性能降低最小化并提高电平转换速度。 构成：响应于输入信号（IN）的上升沿，电平转换部分（110）输出具有与输入信号电平不同的电平的电平转换信号（OUT）。 延迟部分（120）延迟电平转换部分（110）的电平转换信号（OUT）。 自复位部件（130）响应于延迟电平转换信号产生复位信号。 电平转换信号（OUT）的脉冲宽度基于复位信号由所建立的延迟和内部操作延迟之和建立。

公开(公告)号：KR1020030008415A

公开(公告)日：2003-01-29

申请号：KR1020010043049

申请日：2001-07-18

Applicant: 삼성전자주식회사

Inventor： 박정우 ,  조욱래 ,  김남석

IPC: G11C8/00

CPC classification number: H03L7/0805 ,  H03L7/07 ,  H03L7/0812

Abstract: PURPOSE: An internal clock generating circuit is provided to generate an internal clock signal synchronized with an external clock signal and enabling data to be sampled when skew arises between an input cock signal and data. CONSTITUTION: A digital-controlled DLL(Delay Locked Loop) consists of the first delay adjusting circuit(100) and the second delay adjusting circuit(200). The first delay adjusting circuit(100) generates the first clock signal having time delay of T/2(T is a period of an input clock signal) to the input clock, and generates a variable delay signal. The second delay adjusting circuit(200) operates responsive to the variable delay control signal, and generates the second clock signal as an internal clock signal. The second clock signal has time delay over T/2 to the input clock at an initial state and time delay of T to the input clock.

Abstract translation: 目的：提供内部时钟发生电路，以产生与外部时钟信号同步的内部时钟信号，并且在输入开关信号和数据之间出现偏斜时使能数据被采样。 构成：数字控制DLL（延迟锁定环路）由第一延迟调整电路（100）和第二延迟调整电路（200）组成。 第一延迟调整电路（100）产生具有到输入时钟的T / 2（T是输入时钟信号的周期）的时间延迟的第一时钟信号，并产生可变延迟信号。 第二延迟调整电路（200）响应于可变延迟控制信号而工作，并产生第二时钟信号作为内部时钟信号。 第二个时钟信号在初始状态下对输入时钟T / 2具有时间延迟，对输入时钟的时间延迟为T。

公开(公告)号：KR100356576B1

公开(公告)日：2002-10-18

申请号：KR1020000054161

申请日：2000-09-15

Applicant: 삼성전자주식회사

Inventor： 김남석 ,  조욱래

IPC: G11C7/10

Abstract: 데이터의 송신이나 수신시 전송라인의 특성 임피던스(Z0)가 수시로 변화되는 경우에 임피던스 매칭을 제대로 수행하기 어려운 문제를 해결하기 위하여 원하는 값만큼의 송수신 임피던스를 프로그래머블하게 세팅할 수 있는 반도체 장치가 개시되어 있다. 그러한 반도체 장치는, 입출력 패드에 병렬로 배치되며 대응되는 제어신호에 응답하는 복수의 임피던스 소자들을 갖는 입력 터미네이션 회로 겸용의 복수의 출력드라이버와; 양방향 데이터 통신시에 상기 패드에 연결된 전송라인의 특성임피던스 변화에 따라 프로그래머블하게 세팅되는 디지털 코딩신호를 상기 제어신호로서 출력함에 의해, 상기 각 출력드라이버내의 임피던스 소자들이 선택적으로 제어되도록 하여 임피던스 매칭을 적응적으로 행하는 제어부를 구비한다.

公开(公告)号：KR1020020042093A

公开(公告)日：2002-06-05

申请号：KR1020000071832

申请日：2000-11-30

Applicant: 삼성전자주식회사

Inventor： 김남석 ,  조욱래

IPC: H03H3/00

CPC classification number: G05F1/46

Abstract: PURPOSE: An impedance control circuit is provided to reduce an error of a circuit when internal impedance generated according to an external resistance. CONSTITUTION: The impedance control circuit includes a comparator(111) and a reference voltage source(1/2VDDQ). A constant current source is connected with an impedance detector(113) which is grounded. An output generated from the constant current source is inputted to the comparator(111). The output of the comparator is feedback through a counter(112) and the impedance detector(113). When a current generated from the constant current source is inputted to the impedance detector(113), the comparator(111) compares the current with the reference voltage generated from reference voltage source(1/2VDDQ), such that the counter(112) generates an impedance code according to the comparison result.

Abstract translation: 目的：提供阻抗控制电路，以根据外部电阻产生的内部阻抗减小电路的误差。 构成：阻抗控制电路包括比较器（111）和参考电压源（1 / 2VDDQ）。 恒流源与接地的阻抗检测器（113）连接。 从恒流源产生的输出被输入到比较器（111）。 比较器的输出通过计数器（112）和阻抗检测器（113）反馈。 当从恒定电流源产生的电流被输入到阻抗检测器（113）时，比较器（111）将电流与从参考电压源（1 / 2VDDQ）产生的参考电压进行比较，使得计数器（112）产生 根据比较结果的阻抗代码。