公开(公告)号：DK2769382T3

公开(公告)日：2018-07-16

申请号：DK12871181

申请日：2012-11-15

Applicant: IBM

Inventor： BRADBURY JONATHAN DAVID ,  GSCHWIND MICHAEL KARL ,  SCHWARZ ERIC MARK ,  SLEGEL TIMOTHY ,  JACOBI CHRISTIAN

IPC: G06F9/30

公开(公告)号：AU2015238665B2

公开(公告)日：2018-01-18

申请号：AU2015238665

申请日：2015-03-16

Applicant: IBM

Inventor： GREINER DAN ,  FARRELL MARK ,  OSISEK DAMIAN LEO ,  SCHMIDT DONALD WILLIAM ,  BUSABA FADI YUSUF ,  KUBALA JEFFREY PAUL ,  BRADBURY JONATHAN DAVID ,  HELLER LISA CRANTON ,  SLEGEL TIMOTHY ,  GAINEY JR CHARLES

IPC: G06F9/50 ,  G06F9/38

Abstract: A computer system includes a configuration with a core configurable between a single thread (ST) mode and a multithreading (MT) mode. The ST mode addresses a primary thread and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. A multithreading facility is configured to control utilization of the configuration to perform a method that includes accessing the primary thread in the ST mode using a core address value and switching from the ST mode to the MT mode. The primary thread or one of the one or more secondary threads is accessed in the MT mode using an expanded address value, where the expanded address value includes the core address value concatenated with a thread address value.

公开(公告)号：DE112015003584T5

公开(公告)日：2017-05-24

申请号：DE112015003584

申请日：2015-09-15

Applicant: IBM

Inventor： BRADBURY JONATHAN DAVID ,  CARLOUGH STEVEN ,  COPELAND REID ,  MITRAN MARCEL

IPC: G06F9/30 ,  G06F5/00 ,  G06F9/00

Abstract: Ein Verfahren zum Ausführen eines Maschinenbefehls wird bereitgestellt, um Daten von einem dezimalen Gleitkommaformat zu einem gepackten Dezimalformat umzusetzen. Bei dem Verfahren werden Daten in einem dezimalen Gleitkommaformat von einem oder mehreren Registern eines Prozessors gelesen, der zum Zweck des Datenaustauschs mit einem Speicher verbunden ist. Bei dem Verfahren werden die Daten, die in dem dezimalen Gleitkommaformat vorliegen, in ein gepacktes Dezimalformat umgesetzt. Bei dem Verfahren werden die Daten, die in das gepackte Dezimalformat umgesetzt wurden, in den Speicher geschrieben.

公开(公告)号：AU2013375140B2

公开(公告)日：2017-03-23

申请号：AU2013375140

申请日：2013-12-06

Applicant: IBM

Inventor： BRADBURY JONATHAN DAVID ,  SCHWARZ ERIC MARK ,  SLEGEL TIMOTHY ,  GSCHWIND MICHAEL KARL

IPC: G06F17/16

Abstract: Vector exception handling is facilitated. A vector instruction is executed that operates on one or more elements of a vector register. When an exception is encountered during execution of the instruction, a vector exception code is provided that indicates a position within the vector register that caused the exception. The vector exception code also includes a reason for the exception.

公开(公告)号：AU2015330266A1

公开(公告)日：2017-03-09

申请号：AU2015330266

申请日：2015-09-14

Applicant: IBM

Inventor： FARRELL MARK ,  HELLER LISA ,  KUBALA JEFFREY PAUL ,  SCHMIDT DONALD WILLIAM ,  GREINER DAN ,  SLEGEL TIMOTHY ,  BUSABA FADI YUSUF ,  OSISEK DAMIAN ,  BRADBURY JONATHAN DAVID ,  LEHNERT FRANK ,  NERZ BERND ,  JACOBI CHRISTIAN

IPC: G06F9/455 ,  G06F9/48

Abstract: A system and method of implementing a modified priority routing of an input/output (I/O) interruption. The system and method determines whether the I/O interruption is pending for a core and whether any of a plurality of guest threads of the core is enabled for guest thread processing of the interruption in accordance with the determining that the I/O interruption is pending. Further, the system and method determines whether at least one of the plurality of guest threads enabled for guest thread processing is in a wait state and, in accordance with the determining that the at least one of the plurality of guest threads enabled for guest thread processing is in the wait state, routes the I/O interruption to a guest thread enabled for guest thread processing and in the wait state.

公开(公告)号：SG11201606093QA

公开(公告)日：2016-08-30

申请号：SG11201606093Q

申请日：2015-03-16

Applicant: IBM

Inventor： HELLER LISA CRANTON ,  BRADBURY JONATHAN DAVID ,  KUBALA JEFFREY PAUL ,  FARRELL MARK ,  OSISEK DAMIAN LEO ,  GREINER DAN ,  SLEGEL TIMOTHY ,  BUSABA FADI YUSUF ,  SCHMIDT DONALD WILLIAM

IPC: G06F9/455 ,  G06F9/50

公开(公告)号：SG11201606089QA

公开(公告)日：2016-08-30

申请号：SG11201606089Q

申请日：2015-03-16

Applicant: IBM

Inventor： GREINER DAN ,  FARRELL MARK ,  OSISEK DAMIAN LEO ,  SCHMIDT DONALD WILLIAM ,  BUSABA FADI YUSUF ,  KUBALA JEFFREY PAUL ,  BRADBURY JONATHAN DAVID ,  HELLER LISA CRANTON ,  SLEGEL TIMOTHY

IPC: G06F9/50 ,  G06F9/38

Abstract: Embodiments relate to address expansion and contraction in a multithreading computer system. According to one aspect, a computer implemented method for address adjustment in a configuration is provided. The configuration includes a core configurable between an ST mode and an MT mode, where the ST mode addresses a primary thread and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. The primary thread is accessed in the ST mode using a core address value. Switching from the ST mode to the MT mode is performed. The primary thread or one of the one or more secondary threads is accessed in the MT mode using an expanded address value. The expanded address value includes the core address value concatenated with a thread address value.

公开(公告)号：ZA201406610B

公开(公告)日：2016-05-25

申请号：ZA201406610

申请日：2014-09-09

Applicant: IBM

Inventor： SCHWARZ ERIK MARK ,  GSCHWIND MICHAEL KARL ,  JACOBI CHRISTIAN ,  SLEGEL TOMOTHY ,  BRADBURY JONATHAN DAVID

Abstract: A Load to Block Boundary instruction is provided that loads a variable number of bytes of data into a register while ensuring that a specified memory boundary is not crossed. The boundary may be specified a number of ways, including, but not limited to, a variable value in the instruction text, a fixed instruction text value encoded in the opcode, or a register based boundary.

公开(公告)号：GB2525356B

公开(公告)日：2016-03-23

申请号：GB201514700

申请日：2014-01-07

Applicant: IBM

Inventor： BRADBURY JONATHAN DAVID ,  SCHWARZ ERIC MARK

IPC: G06F9/30

公开(公告)号：CA2940905A1

公开(公告)日：2015-10-01

申请号：CA2940905

申请日：2015-03-19

Applicant: IBM

Inventor： GREINER DAN ,  FARRELL MARK ,  OSISEK DAMIAN LEO ,  SCHMIDT DONALD WILLIAM ,  BUSABA FADI YUSUF ,  KUBALA JEFFREY PAUL ,  BRADBURY JONATHAN DAVID ,  HELLER LISA CRANTON ,  SLEGEL TIMOTHY ,  GAINEY CHARLES JR ,  JACOBI CHRISTIAN

IPC: G06F9/46 ,  G06F9/50

Abstract: Embodiments relate to dynamic enablement of multithreading. According to an aspect, a computer system includes a configuration with a core configurable between a single thread (ST) mode and a multithreading (MT) mode. The ST mode addresses a primary thread, and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. The computer system also includes a multithreading facility configured to control the configuration to perform a method. The method includes executing in the primary thread in the ST mode, an MT mode setting instruction. A number of threads requested is obtained from a location specified by the MT mode setting instruction. Based on determining that the number of threads requested indicates multiple threads, the MT mode is enabled to execute the multiple threads including the primary thread and the one or more secondary threads.