公开(公告)号：ZA201605466B

公开(公告)日：2017-08-30

申请号：ZA201605466

申请日：2016-08-05

Applicant: IBM

Inventor： GAINEY JR CHARLES (DECEASED) ,  SLEGEL TIMOTHY ,  HELLER LISA CRANTON ,  BRADBURY JONATHAN DAVID ,  KUBALA JEFFREY PAUL ,  BUSABA FADI YUSUF ,  SCHMIDT DONALD WILLIAM ,  OSISEK DAMIAN LEO ,  FARRELL MARK ,  GREINER DAN

Abstract: Embodiments relate to thread context restoration. One aspect is a multithreading computer system including a configuration with a core configurable between a single thread (ST) mode and a multithreading (MT) mode. The ST mode addresses a primary thread and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. A multithreading facility is configured to control utilization of the configuration to perform a method including disabling one or more secondary threads based on switching from MT mode to ST mode. A thread context of secondary threads is made unavailable to programs. Based on a last-set program-specified maximum thread-id indicating MT, the thread context is obtained by a) executing a set MT instruction to resume the MT mode, and b) based on being in the resumed MT mode, accessing the thread context.

公开(公告)号：BR112014022725A2

公开(公告)日：2017-06-20

申请号：BR112014022725

申请日：2013-03-07

Applicant: IBM

Inventor： BRADBURY JONATHAN DAVID ,  GSCHWIND MICHAEL KARL ,  SLEGEL TIMOTHY ,  SCHWARZ ERIC MARK ,  JACOBI CHRISTIAN

公开(公告)号：SI2834736T1

公开(公告)日：2017-04-26

申请号：SI201230900

申请日：2012-11-22

Applicant: IBM

Inventor： GREINER DAN ,  JACOBI CHRISTIAN ,  SLEGEL TIMOTHY

IPC: G06F9/00

公开(公告)号：SG11201701614WA

公开(公告)日：2017-03-30

申请号：SG11201701614W

申请日：2015-09-14

Applicant: IBM

Inventor： FARRELL MARK ,  HELLER LISA ,  KUBALA JEFFREY PAUL ,  SCHMIDT DONALD WILLIAM ,  GREINER DAN ,  SLEGEL TIMOTHY ,  BUSABA FADI YUSUF ,  OSISEK DAMIAN ,  BRADBURY JONATHAN DAVID ,  LEHNERT FRANK ,  NERZ BERND ,  JACOBI CHRISTIAN

IPC: G06F9/48 ,  G06F9/455

Abstract: A system and method of implementing a modified priority routing of an input/output (I/O) interruption. The system and method determines whether the I/O interruption is pending for a core and whether any of a plurality of guest threads of the core is enabled for guest thread processing of the interruption in accordance with the determining that the I/O interruption is pending. Further, the system and method determines whether at least one of the plurality of guest threads enabled for guest thread processing is in a wait state and, in accordance with the determining that the at least one of the plurality of guest threads enabled for guest thread processing is in the wait state, routes the I/O interruption to a guest thread enabled for guest thread processing and in the wait state.

公开(公告)号：CA2701093C

公开(公告)日：2016-10-11

申请号：CA2701093

申请日：2009-01-07

Applicant: IBM

Inventor： GREINER DAN ,  SLEGEL TIMOTHY

IPC: G06F9/312

Abstract: In a method of operating a computer system there is provided a facility and cache machine instruction of a computer architecture for specifying a target cache cache-level and a target cache attribute of interest for obtaining a cache attribute of one or more target caches. The requested cache attribute of the target cache(s) in saved in a register.

公开(公告)号：BRPI0906424A2

公开(公告)日：2016-10-11

申请号：BRPI0906424

申请日：2009-01-07

Applicant: IBM

Inventor： GREINER DAN ,  SLEGEL TIMOTHY

IPC: G06F9/312

公开(公告)号：AU2012382779B2

公开(公告)日：2016-09-29

申请号：AU2012382779

申请日：2012-11-26

Applicant: IBM

Inventor： GREINER DAN ,  SLEGEL TIMOTHY ,  JACOBI CHRISTIAN

IPC: G06F12/00

Abstract: Constrained transactional processing is provided. A constrained transaction is initiated by execution of a Transaction Begin constrained instruction. The constrained transaction has a number of restrictions associated therewith. Absent violation of a restriction, the constrained transaction is to complete. If an abort condition is encountered, the transaction is re-executed starting at the Transaction Begin instruction. Violation of a restriction may cause an interrupt.

公开(公告)号：DE112015000223T5

公开(公告)日：2016-08-18

申请号：DE112015000223

申请日：2015-03-11

Applicant: IBM

Inventor： GREINER DAN ,  SLEGEL TIMOTHY ,  SCHMIDT DONALD WILLIAM ,  MITRAN MARCEL ,  JACOBI CHRISTIAN

IPC: G06F9/455 ,  G06F9/30 ,  G06F9/38

Abstract: Eine Einrichtung zum Beenden von bedingten Befehlen wird bereitgestellt, die ermöglicht, dass ein Ausführen eines Befehls verzögert wird. Beim Ausführen des Maschinenbefehls wird ein Operand erhalten, und es wird ermittelt, ob der Operand eine vorgegebene Beziehung in Bezug auf einen Wert hat. Auf der Grundlage des Feststellens, dass der Operand die vorgegebene Beziehung in Bezug auf einen Wert nicht hat, werden Erhalten und Ermitteln wiederholt. Auf der Grundlage des Feststellens, dass der Operand die vorgegebene Beziehung in Bezug auf einen Wert hat, findet das Ausführen des Befehls statt. Erhalten des Operanden, Ermitteln, ob der Operand die vorgegebene Beziehung hat, Wiederholen von Erhalten und Ermitteln auf der Grundlage des Feststellens, dass der Operand die vorgegebene Beziehung in Bezug auf den Wert nicht hat, und Ausführen des Befehls auf der Grundlage des Feststellens, dass der Operand die vorgegebene Beziehung in Bezug auf den Wert hat, werden als Teil eines einzigen Befehls ausgeführt, der einen Operationscode enthält.

公开(公告)号：AU2015238706A1

公开(公告)日：2016-08-04

申请号：AU2015238706

申请日：2015-03-06

Applicant: IBM

Inventor： HELLER LISA CRANTON ,  KUBALA JEFFREY PAUL ,  BUSABA FADI YUSUF ,  BRADBURY JONATHAN DAVID ,  FARRELL MARK ,  OSISEK DAMIAN LEO ,  GREINER DAN ,  SLEGEL TIMOTHY ,  SCHMIDT DONALD WILLIAM ,  GAINEY CHARLES ,  JACOBI CHRISTIAN

IPC: G06F9/48 ,  G06F9/30 ,  G06F9/50

Abstract: Embodiments relate to multithreading in a computer. An aspect is a computer including a configuration having a core which includes physical threads and is operable in single thread (ST) and multithreading (MT) modes. The computer also includes a host program configured to execute in the ST mode on the core to issue a start-virtual-execution (start-VE) instruction to dispatch a guest entity which includes a guest virtual machine (VM). The start-VE instruction is executed by the core and includes obtaining a state description, having a guest state, from a location specified by the start-VE instruction. The execution includes determining, based on the guest state, whether the guest entity includes a single guest thread or multiple guest threads, and starting the guest threads in the MT mode or ST mode based on the guest state and a determination of whether the guest entity includes a single guest thread or multiple guest threads.

公开(公告)号：MX340052B

公开(公告)日：2016-06-22

申请号：MX2015009458

申请日：2013-12-06

Applicant: IBM

Inventor： SLEGEL TIMOTHY ,  SCHWARZ ERIC MARK ,  BRADBURY JONATHAN DAVID ,  GSCHWIND MICHAEL KARL

IPC: G06F17/16

Abstract: Se facilita el manejo de la excepción del vector. Se ejecuta una instrucción vectorial que opera en uno o más elementos de un registro del vector. Cuando una excepción se encuentra durante la ejecución de la instrucción, se proporciona un código de excepción del vector, que indica una posición dentro del registro del vector que causó la excepción. El código de excepción del vector también incluye una razón para la excepción.