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    Method of Triggering Avalanche Breakdown in a Semiconductor Device
    82.
    发明申请
    Method of Triggering Avalanche Breakdown in a Semiconductor Device 有权
    触发半导体器件中的雪崩故障的方法

    公开(公告)号：US20160225932A1

    公开(公告)日：2016-08-04

    申请号：US15009271

    申请日：2016-01-28

    Applicant: Infineon Technologies AG

    Inventor： Joost Willemen ,  Michael Mayerhofer ,  Ulrich Glaser ,  Yiqun Cao ,  Andreas Meiser ,  Magnus-Maria Hell ,  Matthias Stecher ,  Julien Lebon

    IPC: H01L31/173 ,  H01L27/15 ,  H01L27/06 ,  H01L29/808 ,  H02H3/20 ,  H01L27/02

    CPC classification number: H01L31/173 ,  H01L27/0255 ,  H01L27/0629 ,  H01L27/15 ,  H01L29/808 ,  H02H3/20

    Abstract: A method of triggering avalanche breakdown in a semiconductor device includes providing an electrical coupling and an optical coupling between an auxiliary semiconductor device configured to emit radiation and the semiconductor device including a pn junction between a first layer of a first conductivity type buried below a surface of a semiconductor body and a doped semiconductor region of a second conductivity type disposed between the surface and the first layer. The electrical and optical coupling includes triggering emission of radiation by the auxiliary semiconductor device and triggering avalanche breakdown in the semiconductor device by absorption of the radiation in the semiconductor device.

    Abstract translation: 一种触发半导体器件中的雪崩击穿的方法包括提供电耦合和配置成发射辐射的辅助半导体器件之间的光耦合，该半导体器件包括埋在第一导电类型的第一层之下的pn结， 设置在表面和第一层之间的半导体本体和第二导电类型的掺杂半导体区域。 电耦合和光耦合包括触发由辅助半导体器件发射的辐射，并通过吸收半导体器件中的辐射来触发半导体器件中的雪崩击穿。

    Semiconductor device in a semiconductor substrate and method of manufacturing a semiconductor device in a semiconductor substrate
    83.
    发明授权
    Semiconductor device in a semiconductor substrate and method of manufacturing a semiconductor device in a semiconductor substrate 有权
    半导体衬底中的半导体器件和半导体衬底中的半导体器件的制造方法

    公开(公告)号：US09397092B2

    公开(公告)日：2016-07-19

    申请号：US14813738

    申请日：2015-07-30

    Applicant: Infineon Technologies AG

    Inventor： Andreas Meiser ,  Markus Zundel ,  Till Schloesser

    IPC: H01L27/08 ,  H01L49/02 ,  H01L21/768 ,  H01L29/40 ,  H01L27/06 ,  H01L21/00

    CPC classification number: H01L27/0805 ,  H01L21/7687 ,  H01L21/76877 ,  H01L27/0629 ,  H01L28/40 ,  H01L28/60 ,  H01L28/90 ,  H01L29/407

    Abstract: A semiconductor device in a semiconductor substrate includes a trench in a first main surface of the semiconductor substrate. The trench includes a first trench portion extending in a first direction and a second trench portion extending in the first direction. The first trench portion is connected with the second trench portion in a lateral direction. The first trench portion and the second trench portion are arranged one after the other along the first direction. The semiconductor device further includes a trench conductive structure having a conductive material disposed in the first trench portion, and a trench capacitor structure having a capacitor dielectric and a first capacitor electrode disposed in the second trench portion. The first capacitor electrode includes a layer lining a sidewall of the second trench portion.

    Abstract translation: 半导体衬底中的半导体器件包括在半导体衬底的第一主表面中的沟槽。 沟槽包括沿第一方向延伸的第一沟槽部分和沿第一方向延伸的第二沟槽部分。 第一沟槽部分沿横向方向与第二沟槽部分连接。 第一沟槽部分和第二沟槽部分沿着第一方向一个接一个布置。 半导体器件还包括具有设置在第一沟槽部分中的导电材料的沟槽导电结构，以及具有电容器电介质的沟槽电容器结构和设置在第二沟槽部分中的第一电容器电极。 第一电容器电极包括衬在第二沟槽部分的侧壁上的层。

    CIRCUIT AND METHOD FOR MEASURING A CURRENT
    85.
    发明申请
    CIRCUIT AND METHOD FOR MEASURING A CURRENT 审中-公开
    用于测量电流的电路和方法

    公开(公告)号：US20160164279A1

    公开(公告)日：2016-06-09

    申请号：US14564172

    申请日：2014-12-09

    Applicant: Infineon Technologies AG

    Inventor： Michael Asam ,  Andreas Meiser ,  Steffen Thiele

    IPC: H02H9/02 ,  G01R19/165 ,  H03K19/0185

    CPC classification number: G01R19/16519 ,  G01R19/16538 ,  H02H3/087 ,  H03K19/018507

    Abstract: Circuits, switches with over-current protection and methods for measuring a current are described herein. A circuit configured to provide a current from a supply voltage to a load includes a first transistor, a second transistor, and a detecting circuit. The first transistor has a larger active area than the second transistor. The detecting circuit is configured to detect a current through the second transistor. A same voltage is applied between a control terminal of the first transistor and a first controlled terminal of the first transistor and is applied between a control terminal of the second transistor and a first controlled terminal of the second transistor. The detecting circuit is coupled to the second controlled terminal of the second transistor and is coupled to the supply voltage.

    Abstract translation: 这里描述了具有过电流保护的电路，开关和用于测量电流的方法。 配置成将电流从电源电压提供给负载的电路包括第一晶体管，第二晶体管和检测电路。 第一晶体管具有比第二晶体管更大的有源面积。 检测电路被配置为检测通过第二晶体管的电流。 在第一晶体管的控制端子和第一晶体管的第一受控端子之间施加相同的电压，并施加在第二晶体管的控制端子和第二晶体管的第一受控端子之间。 检测电路耦合到第二晶体管的第二受控端并耦合到电源电压。

    Method of Manufacturing a Semiconductor Device
    88.
    发明申请
    Method of Manufacturing a Semiconductor Device 有权
    制造半导体器件的方法

    公开(公告)号：US20140363940A1

    公开(公告)日：2014-12-11

    申请号：US14464849

    申请日：2014-08-21

    Applicant: Infineon Technologies AG

    Inventor： Andreas Meiser ,  Franz Hirler ,  Christian Kampen

    IPC: H01L21/383 ,  H01L29/40 ,  H01L29/66

    CPC classification number: H01L21/383 ,  H01L29/402 ,  H01L29/407 ,  H01L29/66803 ,  H01L29/7816 ,  H01L29/785

    Abstract: A transistor is formed by forming a ridge including a first ridge portion and a second ridge portion in a semiconductor substrate, the ridge extending along a first direction, forming a source region, a drain region, a channel region, a drain extension region and a gate electrode adjacent to the channel region, in the ridge, doping the channel region with dopants of a first conductivity type, and doping the source region and the drain region with dopants of a second conductivity type. Forming the drain extension region includes forming a core portion doped with the first conductivity type in the second ridge portion, and forming the drain extension region further includes forming a cover portion doped with the second conductivity type, the cover portion being formed so as to be adjacent to at least one or two sidewalls of the second ridge portion.

    Abstract translation: 晶体管通过在半导体衬底中形成包括第一脊部分和第二脊部分的脊而形成，所述脊部沿着第一方向延伸，形成源极区域，漏极区域，沟道区域，漏极延伸区域和 栅极与沟道区相邻，在脊中，掺杂具有第一导电类型的掺杂剂的沟道区，并用第二导电类型的掺杂剂掺杂源区和漏区。 形成漏极延伸区域包括在第二脊部中形成掺杂有第一导电类型的芯部分，并且形成漏极延伸区域还包括形成掺杂有第二导电类型的覆盖部分，盖部分形成为 邻近第二脊部分的至少一个或两个侧壁。

    SEMICONDUCTOR COMPONENT AND METHODS FOR PRODUCING A SEMICONDUCTOR COMPONENT
    89.
    发明申请
    SEMICONDUCTOR COMPONENT AND METHODS FOR PRODUCING A SEMICONDUCTOR COMPONENT 有权
    半导体元件的制造方法和半导体元件的制造方法

    公开(公告)号：US20140141608A1

    公开(公告)日：2014-05-22

    申请号：US14166090

    申请日：2014-01-28

    Applicant: Infineon Technologies AG

    Inventor： Andreas Meiser ,  Walter Hartner ,  Hermann Gruber ,  Dietrich Bonart ,  Thomas Gross

    IPC: H01L21/768

    CPC classification number: H01L21/76802 ,  H01L21/76286 ,  H01L21/76877 ,  H01L21/84 ,  H01L27/1203

    Abstract: A method for producing a semiconductor component with a semiconductor body includes providing a substrate of a first conductivity type. A buried semiconductor layer of a second conductivity type is provided on the substrate. A functional unit semiconductor layer is provided on the buried semiconductor layer. At least one trench, which reaches into the substrate, is formed in the semiconductor body. An insulating layer is formed, which covers inner walls of the trench and electrically insulates the trench interior from the functional unit semiconductor layer and the buried semiconductor layer, the insulating layer having at least one opening in the region of the trench bottom. The at least one trench is filled with an electrically conductive semiconductor material of the first conductivity type, wherein the electrically conductive semiconductor material forms an electrical contact from a surface of the semiconductor body to the substrate.

    Abstract translation: 一种制造具有半导体本体的半导体部件的方法，包括提供第一导电型的基板。 在基板上设置第二导电类型的掩埋半导体层。 功能单元半导体层设置在掩埋半导体层上。 至少一个到达衬底的沟槽形成在半导体本体中。 形成绝缘层，其覆盖沟槽的内壁，并使沟槽内部与功能单元半导体层和埋入半导体层电绝缘，绝缘层在沟槽底部的区域中具有至少一个开口。 所述至少一个沟槽填充有第一导电类型的导电半导体材料，其中所述导电半导体材料形成从所述半导体主体的表面到所述衬底的电接触。

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