公开(公告)号：US20230395697A1

公开(公告)日：2023-12-07

申请号：US17831800

申请日：2022-06-03

Applicant: Intel Corporation

Inventor： Nicole K. Thomas ,  Munzarin F. Qayyum ,  Marko Radosavljevic ,  Cheng-Ying Huang ,  Willy Rachmady ,  Rohit Galatage ,  Jami A. Wiedemer ,  David Bennett ,  Dincer Unluer ,  Venkata Aditya Addepalli

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L21/8238

CPC classification number: H01L29/66545 ,  H01L29/42392 ,  H01L29/78696 ,  H01L29/0669 ,  H01L21/823807

Abstract: A semiconductor structure includes a second device stacked over a first device. In an example, the first device includes (i) a first source region, (ii) a first drain region, (iii) a body including a semiconductor material extending laterally from the first source region to the first drain region, and (iv) a first gate structure at least in part wrapped around the body. The body can be, for instance, a nanoribbon, nanosheet, or nanowire. In an example, the second device comprises (i) a second source region, (ii) a second drain region, and (iii) a second gate structure at least in part laterally between the second source region and the second drain region. In an example, the second device lacks a continuous body extending laterally from the second source region to the second drain region.

公开(公告)号：US11764104B2

公开(公告)日：2023-09-19

申请号：US16454553

申请日：2019-06-27

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Gilbert Dewey ,  Jack T. Kavalieros ,  Aaron Lilak ,  Ehren Mannebach ,  Patrick Morrow ,  Anh Phan ,  Willy Rachmady ,  Hui Jae Yoo

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/02 ,  H01L21/225 ,  H01L21/265 ,  H01L21/266 ,  H01L21/311 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L21/76264 ,  H01L21/02236 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/2253 ,  H01L21/2255 ,  H01L21/266 ,  H01L21/26533 ,  H01L21/31111 ,  H01L21/76267 ,  H01L29/0649 ,  H01L29/7853

Abstract: Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes to form volumes of oxide within a fin, such as a Si fin. In embodiments, this may be accomplished by applying a catalytic oxidant material on a side of a fin and then annealing to form a volume of oxide. In embodiments, this may be accomplished by using a plasma implant technique or a beam-line implant technique to introduce oxygen ions into an area of the fin and then annealing to form a volume of oxide. Processes described here may be used manufacture a transistor, a stacked transistor, or a three-dimensional (3-D) monolithic stacked transistor.

公开(公告)号：US11756998B2

公开(公告)日：2023-09-12

申请号：US17576765

申请日：2022-01-14

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Tahir Ghani ,  Jack Kavalieros ,  Anand Murthy ,  Harold Kennel ,  Gilbert Dewey ,  Matthew Metz ,  Willy Rachmady ,  Sean Ma ,  Nicholas Minutillo

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/205 ,  H01L29/417 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78

CPC classification number: H01L29/0684 ,  H01L21/02543 ,  H01L21/02546 ,  H01L29/0669 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/205 ,  H01L29/41758 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/7851

Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device having a channel area including a channel III-V material, and a source area including a first portion and a second portion of the source area. The first portion of the source area includes a first III-V material, and the second portion of the source area includes a second III-V material. The channel III-V material, the first III-V material and the second III-V material may have a same lattice constant. Moreover, the first III-V material has a first bandgap, and the second III-V material has a second bandgap, the channel III-V material has a channel III-V material bandgap, where the channel material bandgap, the second bandgap, and the first bandgap form a monotonic sequence of bandgaps. Other embodiments may be described and/or claimed.

公开(公告)号：US20230197569A1

公开(公告)日：2023-06-22

申请号：US17556711

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Cheng-Ying Huang ,  Nicole K. Thomas ,  Marko Radosavljevic ,  Patrick Morrow ,  Ashish Agrawal ,  Willy Rachmady ,  Seung Hoon Sung ,  Christopher M. Neumann

IPC: H01L23/48 ,  H01L27/092 ,  H01L29/06 ,  H01L29/786 ,  H01L29/423 ,  H01L21/8234

CPC classification number: H01L23/481 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/78696 ,  H01L29/42392 ,  H01L21/823475

Abstract: Techniques are provided herein to form semiconductor devices having a frontside and backside contact in an epi region of a stacked transistor configuration. In one example, an n-channel device and a p-channel device may both be GAA transistors where the n-channel device is located vertically above the p-channel device (or vice versa). Source or drain regions are adjacent to both ends of the n-channel device and the p-channel device. Deep and narrow contacts may be formed from both the frontside and the backside of the integrated circuit through the stacked source or drain regions. The contacts may physically contact each other to form a combined contact that extends through an entirety of the stacked source or drain regions. The higher contact area provided to both source or drain regions provides a more robust ohmic contact with a lower contact resistance compared to previous contact architectures.

公开(公告)号：US20230178552A1

公开(公告)日：2023-06-08

申请号：US17543049

申请日：2021-12-06

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Patrick Morrow ,  Arunshankar Venkataraman ,  Sean T. Ma ,  Willy Rachmady ,  Nicole K. Thomas ,  Marko Radosavljevic ,  Jack T. Kavalieros

IPC: H01L27/092 ,  H01L23/535 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L27/0922 ,  H01L21/0259 ,  H01L21/82385 ,  H01L21/823807 ,  H01L21/823871 ,  H01L23/535 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696

Abstract: Techniques are provided herein to form semiconductor devices having a stacked transistor configuration. An n-channel device and a p-channel device may both be gate-all-around (GAA) transistors each having any number of nanoribbons extending in the same direction where one device is located vertically above the other device. According to some embodiments, the n-channel device and the p-channel device conductively share the same gate, and a width of the gate structure around one device is greater than the width of the gate structure around the other device. According to some other embodiments, the n-channel device and the p-channel device each have a separate gate structure that is isolated from the other using a dielectric layer between them. A gate contact is adjacent to the upper device and contacts the gate structure of the other lower device.

公开(公告)号：US11640961B2

公开(公告)日：2023-05-02

申请号：US16954126

申请日：2018-03-28

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Ravi Pillarisetty ,  Jack T. Kavalieros ,  Aaron D. Lilak ,  Willy Rachmady ,  Rishabh Mehandru ,  Kimin Jun ,  Anh Phan ,  Hui Jae Yoo ,  Patrick Morrow ,  Cheng-Ying Huang ,  Matthew V. Metz

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/78 ,  H01L27/06 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66

Abstract: An integrated circuit structure comprises a lower device layer that includes a first structure comprising a plurality of PMOS transistors. An upper device layer is formed on the lower device layer, wherein the upper device layer includes a second structure comprising a plurality of NMOS transistors having a group III-V material source/drain region.

公开(公告)号：US11557658B2

公开(公告)日：2023-01-17

申请号：US16649592

申请日：2017-12-27

Applicant: INTEL CORPORATION

Inventor： Gilbert Dewey ,  Sean T. Ma ,  Tahir Ghani ,  Willy Rachmady ,  Cheng-Ying Huang ,  Anand S. Murthy ,  Harold W. Kennel ,  Nicholas G. Minutillo ,  Matthew V. Metz

IPC: H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

Abstract: Transistors having a plurality of channel semiconductor structures, such as fins, over a dielectric material. A source and drain are coupled to opposite ends of the structures and a gate stack intersects the plurality of structures between the source and drain. Lateral epitaxial overgrowth (LEO) may be employed to form a super-lattice of a desired periodicity from a sidewall of a fin template structure that is within a trench and extends from the dielectric material. Following LEO, the super-lattice structure may be planarized with surrounding dielectric material to expose a top of the super-lattice layers. Alternating ones of the super-lattice layers may then be selectively etched away, with the retained layers of the super-lattice then laterally separated from each other by a distance that is a function of the super-lattice periodicity. A gate dielectric and a gate electrode may be formed over the retained super-lattice layers for a channel of a transistor.

公开(公告)号：US20220375916A1

公开(公告)日：2022-11-24

申请号：US17323425

申请日：2021-05-18

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Cheng-Ying Huang ,  Ashish Agrawal ,  Gilbert W. Dewey ,  Jack T. Kavalieros ,  Abhishek A. Sharma ,  Willy Rachmady

IPC: H01L25/18 ,  H01L25/065 ,  H01L27/108 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: Described herein are IC devices that include multilayer memory structures bonded to compute logic using low-temperature oxide bonding to realize high-density three-dimensional (3D) dynamic random-access memory (DRAM). An example device includes a compute die, a multilayer memory structure, and an oxide bonding interface coupling the compute die to the multilayer memory structure. The oxide bonding interface includes metal interconnects and an oxide material surrounding the metal interconnects and bonding the compute die to the memory structure.

公开(公告)号：US11444159B2

公开(公告)日：2022-09-13

申请号：US16612259

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Sean T. Ma ,  Gilbert Dewey ,  Willy Rachmady ,  Matthew V. Metz ,  Cheng-Ying Huang ,  Harold W. Kennel ,  Jack T. Kavalieros ,  Anand S. Murthy ,  Tahir Ghani

IPC: H01L29/10 ,  H01L29/205 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78

Abstract: An electronic device comprises a channel layer on a buffer layer on a substrate. The channel layer has a first portion and a second portion adjacent to the first portion. The first portion comprises a first semiconductor. The second portion comprises a second semiconductor that has a bandgap greater than a bandgap of the first semiconductor.

公开(公告)号：US11437405B2

公开(公告)日：2022-09-06

申请号：US16024696

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Patrick Morrow ,  Aaron Lilak ,  Willy Rachmady ,  Anh Phan ,  Ehren Mannebach ,  Hui Jae Yoo ,  Abhishek Sharma ,  Van H. Le ,  Cheng-Ying Huang

IPC: H01L29/78 ,  H01L27/12 ,  H01L21/82 ,  H01L29/786 ,  H01L21/8258

Abstract: Embodiments herein describe techniques for an integrated circuit (IC). The IC may include a first transistor, an insulator layer above the first transistor, and a second transistor above the insulator layer. The first transistor may be a p-type transistor including a channel in a substrate, a first source electrode, and a first drain electrode. A first metal contact may be coupled to the first source electrode, while a second metal contact may be coupled to the first drain electrode. The insulator layer may be next to the first metal contact, and next to the second metal contact. The second transistor may include a second source electrode, and a second drain electrode. The second source electrode may be coupled to the first metal contact, or the second drain electrode may be coupled to the second metal contact. Other embodiments may be described and/or claimed.