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    FAST CONVERGING POWER CONTROL FOR WIRELESS COMMUNICATION SYSTEMS
    81.
    发明专利
    FAST CONVERGING POWER CONTROL FOR WIRELESS COMMUNICATION SYSTEMS 未知

    公开(公告)号：AU2003293440A1

    公开(公告)日：2004-06-30

    申请号：AU2003293440

    申请日：2003-12-04

    Applicant: QUALCOMM INC

    Inventor： OH HYUKJUN ,  BLESSENT LUCA ,  HSU CHIH-PING ,  SHIU DA-SHAN ,  KASTURI NITIN ,  SUBRAHMANYA PARVATHANATHAN

    IPC: H04B7/005

    Abstract: Techniques to quickly adjust an SIR target toward a final value needed to achieve a specified target BLER for a data transmission. The outer loop may be implemented with multiple modes. The SIR target may be maintained fixed in a hold mode, adjusted in large down steps to speed up convergence in an acquisition mode, and adjusted by a small down step and a large up step for good and erased blocks, respectively, in a tracking mode. Various schemes may be used to adjust the SIR target by larger down steps in the acquisition mode. These schemes may be used even if data is transmitted intermittently, the target BLER is set to a low value, and/or one or multiple transport channels are used for data transmission. The SIR target may be boosted by a particular amount upon transitioning from the acquisition mode to the tracking mode.

    LOW LATENCY FREQUENCY SWITCHING
    82.
    发明专利
    LOW LATENCY FREQUENCY SWITCHING 未知

    公开(公告)号：AU2003285122A1

    公开(公告)日：2004-05-25

    申请号：AU2003285122

    申请日：2003-10-31

    Applicant: QUALCOMM INC

    Inventor： MALDONADO DAVID ,  DHALIWAL UPKAR ,  SHIU DA-SHAN ,  ZHANG LI ,  SY EUGENE

    IPC: H03G3/30 ,  H04B1/38

    Abstract: Techniques for improved low latency frequency switching are disclosed. In one embodiment, a controller receives a frequency switch command and generates a frequency switch signal at a time determined in accordance with a system timer. In another embodiment, gain calibration is initiated subsequent to the frequency switch signal delayed by the expected frequency synthesizer settling time. In yet another embodiment, DC cancellation control and gain control are iterated to perform gain calibration, with signaling to control the iterations without need for processor intervention. Various other embodiments are also presented. Aspects of the embodiments disclosed may yield the benefit of reducing latency during frequency switching, allowing for increased measurements at alternate frequencies, reduced time spent on alternate frequencies, and the capacity and throughput improvements that follow from minimization of disruption of an active communication session and improved neighbor selection.

    Scheduling techniques for a packet-access network
    84.
    发明专利
    Scheduling techniques for a packet-access network 未知

    公开(公告)号：AU2003282727A8

    公开(公告)日：2004-04-23

    申请号：AU2003282727

    申请日：2003-10-02

    Applicant: QUALCOMM INC

    Inventor： SHIU DA-SHAN ,  MALLADI DURGA P

    IPC: H04B1/707

    Abstract: Multiple access interference may be substantially removed by introducing a near-far situation in which a near mobile and a far mobile ("near" and "far" based on signal strength) are selected, resources allocated among these and other mobiles, and the data is packetized for transmission during a transmission interval such that the data intended for the far mobile is transmitted along with the data intended for the near mobile. Forward link signals are then appropriately scheduled. Signals intended for the far mobile and the near mobile are decoded from the composite signal received at the near mobile. The signal intended for the far mobile is then removed from the composite signal received at the near mobile.

    ENERGY RETRANSMISSION MINIMISING METHOD AND APPARATUS THEREOF IN ARQ COMMUNICATIONS
    86.
    发明专利
    ENERGY RETRANSMISSION MINIMISING METHOD AND APPARATUS THEREOF IN ARQ COMMUNICATIONS 未知

    公开(公告)号：AU2003265603A1

    公开(公告)日：2004-03-03

    申请号：AU2003265603

    申请日：2003-08-19

    Applicant: QUALCOMM INC

    Inventor： VAYANOS ALKINOOS H ,  MALLADI DURGA PRASAD ,  SHIU DA-SHAN

    IPC: H04B7/005 ,  H04J13/00 ,  H04L1/00 ,  H04L1/16 ,  H04L1/18 ,  H04L1/20 ,  H04W52/26

    Abstract: Systems and techniques are disclosed relating to communications. The systems and techniques involve transmitting to a remote location a first signal at a first energy level followed by a second signal at a second energy level, determining a target transmission energy level as a function of a target quality parameter at the remote location, and computing the second energy level as a function of the target transmission energy level and the first energy level. It is emphasized that this abstract is provided solely to assist a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

    87.
    发明专利
    未知

    公开(公告)号：BR0115491A

    公开(公告)日：2004-02-17

    申请号：BR0115491

    申请日：2001-11-14

    Applicant: QUALCOMM INC

    Inventor： AGRAWAL AVNEESH ,  SHIU DA-SHAN

    IPC: H04B7/005 ,  H04B7/26

    Abstract: In a wireless communication system (10) having a composite transport channel made up of individual transport channels, a method for closed loop power control wherein multiple instances of the outer loop are performed in parallel. The method determines a Signal-to-Interference Ratio (SIR) threshold for the composite channel based on a channel quality metric evaluated for each of the individual channels. In one embodiment the channel quality metric is a Cyclical Redundancy Check (CRC) outcome.

    INTERLEAVER FOR TURBO DECODER
    89.
    发明专利
    INTERLEAVER FOR TURBO DECODER 未知

    公开(公告)号：CA2439573A1

    公开(公告)日：2002-09-06

    申请号：CA2439573

    申请日：2002-02-26

    Applicant: QUALCOMM INC

    Inventor： YAO IWEN ,  SHIU DA-SHAN

    IPC: H03M13/27 ,  H03M13/29 ,  H04L1/00 ,  H04L5/02

    Abstract: Techniques to efficiently generate memory addresses for a Turbo code interleaver using a number of look-up tables. An interleaver includes a storage unit, sets of tables, and an address generator. The storage unit stores K elements for a data packet at locations representative of an RxC array, with the elements being stored in a first (e.g., linear) order and provided in a second (e.g., interleaved) order. A first set of table(s) stor es sequences (e.g., inter-row permutation sequences PA, PB, PC and PD) used to perform row permutation of the array to map from the first order to the seco nd order. A second set of table(s) stores sequences (e.g., intra-row base sequences and prime number sequences) used to perform column permutation. Th e address generator receives a first address for the first order and generates a corresponding second address for the second order based on sequences stored in the tables.

    Data buffer structure for asynchronously received physical channels in a cdma system
    90.
    发明专利
    Data buffer structure for asynchronously received physical channels in a cdma system 未知

    公开(公告)号：AU8850701A

    公开(公告)日：2002-03-22

    申请号：AU8850701

    申请日：2001-08-28

    Applicant: QUALCOMM INC

    Inventor： SHIU DA-SHAN ,  AGRAWAL AVNEESH ,  TERASAWA DAISUKE

    IPC: H03M13/27 ,  H04B1/707

    Abstract: A receiver unit for use in a CDMA system and including a channel processor, a buffer, and a data processor. The channel processor processes samples for one or more physical channels for each time interval to provide symbols. The buffer is operated as a number of memory banks. Each memory bank is associated with a respective time interval and stores symbols associated with that time interval. The data processor retrieves symbols for a particular "traffic" from one or more memory banks and processes the retrieved symbols. For the W-CDMA system, each traffic includes one or more radio frames for a particular transmission time interval. The receiver unit typically further includes a controller that directs the storage and retrieval of symbols to and from the memory banks and a decoder that decodes symbols processed by the data processor. For each time interval, radio frames for physical channels received starting within that time interval can be stored to permutated locations of designated sections of the memory bank. Radio frames associated with a particular CCTrCH can be stored to contiguous sections of the memory bank. Symbols for a particular traffic can be retrieved from one or more memory banks in permutated order.

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