中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

97 records (took 0.049 seconds)

    Method for accessing in reading, writing and programming to a NAND non-volatile memory electronic device monolithically integrated on semiconductor
    81.
    发明公开
    Method for accessing in reading, writing and programming to a NAND non-volatile memory electronic device monolithically integrated on semiconductor 有权
    在读取，写入和擦除非易失性NAND存储器存取方法

    公开(公告)号：EP1788575A1

    公开(公告)日：2007-05-23

    申请号：EP05425814.0

    申请日：2005-11-18

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pascucci, Luigi ,  Rolandi, Paolo

    IPC: G11C8/06 ,  G11C16/08 ,  G11C16/04

    CPC classification number: G11C5/066 ,  G11C7/1018 ,  G11C7/1045 ,  G11C16/0483 ,  G11C16/08 ,  G11C2207/105

    Abstract: The invention relates to a method for accessing, in reading, programming and/or erasing, to a semiconductor integrated non volatile memory device of the Flash EEPROM type with a NAND architecture comprising at least one memory matrix (2) organised in rows or word lines (WL) and columns or bit lines (BL), and wherein, for the memory, a plurality of additional address pins are provided. Advantageously, the method provides both an access protocol of the asynchronous type and a protocol of the extended type allowing to address, directly and in parallel, a memory extended portion by loading an address register associated with said additional pins in two successive clock pulses.
    A third multi-sequential access mode and a parallel additional bus referring to said additional address pins are also provided to allow a double addressing mode, sequential and in parallel.

    Abstract translation: 本发明涉及一种用于访问，在读取，编程和/或擦除，将Flash EEPROM类型的半导体集成电路的非易失性存储器装置与以行或字线中组织NAND架构包含至少一个存储器矩阵（2） （WL）和列线或位线（BL），并worin，对于存储器中，提供的附加的地址引脚复数。 有利的是，该方法提供的两个异步类型的接入协议和扩展类型允许对地址，直接并行，存储器部分通过加载到地址寄存器与所述附加销在两个连续的时钟脉冲相关联的扩展的协议。 因此提供了一种第三多顺序访问模式和并行总线附加参照所述附加地址引脚，以允许双寻址模式，顺序和并行。

    Semiconductor memory system including selection transistors
    84.
    发明公开
    Semiconductor memory system including selection transistors 审中-公开
    Halbleiterspeicher mit Auswahltransistoren

    公开(公告)号：EP1434235A1

    公开(公告)日：2004-06-30

    申请号：EP02425796.6

    申请日：2002-12-24

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pascucci, Luigi

    IPC: G11C16/26 ,  G11C16/04

    CPC classification number: G11C16/26 ,  G11C16/0475

    Abstract: A semiconductor memory system (38) comprising a memory matrix (110) including a plurality of memory cells arranged in rows and columns and connected to a plurality of column lines, each memory cell of the same column having a first and a second terminal connected to a first and a second column line respectively.
    Furthermore, the memory system (38) comprises a first (Main-0) and a second (Main-1) conduction line which can be connected to said first and second column lines, and generating means (41) provided with at least a first (a) and a second (b) output line, making available a first and a second reading/writing voltage to said first and second terminal respectively.
    The memory system (38) is characterized in that it comprises at least a first (Q 1 ) and a second (Q 2 ) selection transistor connected to the same command line (L1) and having corresponding operative terminals connected directly to the first (a) and to the second (b) output lines respectively and corresponding cell terminals connected directly to the first (Main-0) and to the second (Main-1) conduction lines respectively.

    Abstract translation: 一种半导体存储器系统（38），包括存储矩阵（110），所述存储器矩阵包括以行和列排列并连接到多条列线的多个存储器单元，所述同一列的每个存储单元具有第一和第二端子， 分别是第一列和第二列。 此外，存储系统（38）包括可连接到所述第一和第二列线的第一（主0）和第二主（Main-1）导线，以及设置有 至少第一（a）和第二（b）输出线，分别向所述第一和第二端提供第一和第二读/写电压。 存储系统（38）的特征在于，其至少包括连接到相同命令行（L1）的第一（Q1）和第二（Q2）选择晶体管，并具有直接连接到第一 （a）和第二（b）个输出线和分别直接连接到第一（主0）和第二主（Main-1）导线的相应的单元端子。

    Programming method of the memory cells in a multilevel non-volatile memory device
    85.
    发明公开
    Programming method of the memory cells in a multilevel non-volatile memory device 审中-公开
    在einernichtflüchtigenMultibitspeicheranordnung的Speicherzellen程序

    公开(公告)号：EP1365417A1

    公开(公告)日：2003-11-26

    申请号：EP02425293.4

    申请日：2002-05-13

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pascucci, Luigi ,  Rolandi, Paolo ,  Riva, Marco

    IPC: G11C16/10 ,  G11C11/56

    CPC classification number: G11C11/5628

    Abstract: The invention relates to a method for programming a non-volatile memory device of the multi-level type, comprising a plurality of transistor cells grouped into memory words and conventionally provided with gate and drain terminals. The method applies different drain voltage values at different threshold values. Such values are directly proportional to the threshold levels to be attained by the individual memory word bits, and effective to provide for a simultaneous attainment of the levels, in a seeking-to manner, of the levels at the end of a limited number of pulses.
    Advantageously, a constant gate voltage value is concurrently applied to the gate terminals of said cells, such that the cell programming time is unrelated to the threshold level sought.

    Abstract translation: 本发明涉及一种用于对多电平型非易失性存储器件进行编程的方法，包括分组成存储字的多个晶体管单元，并且通常设置有栅极和漏极端子。 该方法在不同的阈值下应用不同的漏极电压值。 这样的值与由各个存储器字位获得的阈值水平成正比，并且有效地提供在寻求方式中同时获得在有限数量的脉冲结束时的电平的电平 。 有利地，恒定栅极电压值同时施加到所述单元的栅极端子，使得单元编程时间与所寻求的阈值水平无关。

    Synchronization circuit for read paths of an electronic memory
    90.
    发明公开
    Synchronization circuit for read paths of an electronic memory 审中-公开
    Schaltungsanordnung zur Lesepfadsynchronisation eines elektronischen Speichers

    公开(公告)号：EP1148508A1

    公开(公告)日：2001-10-24

    申请号：EP00830269.7

    申请日：2000-04-10

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pascucci, Luigi

    IPC: G11C7/00

    CPC classification number: G11C7/1045 ,  G11C7/1042 ,  G11C7/22

    Abstract: A synchronization circuit for read paths of an electronic memory, the memory being divided into two separate banks (EVEN, ODD), each bank comprising sense amplifiers (7, 8) and a counter circuit, comprising:

    a circuit network (30) for managing the equalization of the memory cells of the memory banks, adapted to generate a synchronization signal (EQ-det) for the steps for updating the output buffer (9) of the memory;
    a circuit network (1) for managing the connection between sense amplifiers (7, 8) of the memory and the output buffer (9), the network being driven by the synchronization signal (EQ-det) for the memory output buffer updating steps, by signals (PRI-EV, PRI-ODD) for controlling the selection of the connecting path between the sense amplifier and the output buffer related to the memory bank affected by the read process, and by timing circuits (5) which are adapted to determine the read mode of the memory.

    Abstract translation: 一种用于电子存储器的读取路径的同步电路，所述存储器被分成两个独立的存储体（EVEN，ODD），每个存储体包括读出放大器（7,8）和计数器电路，包括：电路网络（30） 适于产生用于更新存储器的输出缓冲器（9）的步骤的同步信号（EQ-det）的存储器组的存储器单元的均衡; 用于管理存储器的读出放大器（7,8）和输出缓冲器（9）之间的连接的电路网络（1），所述网络由用于存储器输出缓冲器更新步骤的同步信号（EQ-det）驱动， 通过信号（PRI-EV，PRI-ODD），用于控制对读取过程影响的存储体相关的读出放大器和输出缓冲器之间的连接路径的选择，以及定时电路（5），其适于确定 内存的读取模式。

Patent Agency Ranking