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公开(公告)号:US11923350B2
公开(公告)日:2024-03-05
申请号:US18079884
申请日:2022-12-13
Applicant: Unimicron Technology Corp.
Inventor: Ming-Ru Chen , Tzyy-Jang Tseng , Cheng-Chung Lo
CPC classification number: H01L25/167 , H01L33/62 , H01L33/56 , H01L2933/0066
Abstract: A manufacturing method of a light emitting diode (LED) package structure includes the following steps. A carrier is provided. A redistribution layer is formed on the carrier. A plurality of active devices are formed on the carrier. A plurality of LEDs are transferred on the redistribution layer. The LEDs and the active devices are respectively electrically connected to the redistribution layer. The active devices are adapted to drive the LEDs, respectively. A molding compound is formed on the redistribution layer to encapsulate the LEDs. The carrier is removed to expose a bottom surface of the redistribution layer.
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公开(公告)号:US20230400649A1
公开(公告)日:2023-12-14
申请号:US17835990
申请日:2022-06-09
Applicant: Unimicron Technology Corp.
Inventor: John Hon-Shing Lau , Tzyy-Jang Tseng
IPC: G02B6/42
CPC classification number: G02B6/4274 , G02B6/4295 , H01S5/423 , G02B6/4249 , G02B6/4271
Abstract: A package structure includes a circuit board, a package substrate, a fine metal L/S RDL-substrate, an electronic assembly, a photonic assembly, a heat dissipation assembly, and an optical fiber assembly. The package substrate is disposed on and electrically connected to the circuit board. The fine metal L/S RDL-substrate is disposed on and electrically connected to the package substrate. The electronic assembly includes an application specific integrated circuit (ASIC) assembly, an electronic integrated circuit (EIC) assembly, and a photonic integrated circuit (PIC) assembly which are respectively disposed on the fine metal L/S RDL-substrate and electrically connected to the package substrate by the fine metal L/S RDL-substrate. The heat dissipation assembly is disposed on the electronic assembly. The optical fiber assembly is disposed on the package substrate and electrically connected to the package substrate and the PIC assembly. A packaging method of the VCSEL array chip is presented.
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公开(公告)号:US11690173B2
公开(公告)日:2023-06-27
申请号:US17674837
申请日:2022-02-18
Applicant: Unimicron Technology Corp.
Inventor: Tzyy-Jang Tseng , Chin-Sheng Wang , Ra-Min Tain
CPC classification number: H05K1/0298 , H05K1/023 , H05K1/181 , H05K1/185 , H05K1/032 , H05K1/036 , H05K1/092 , H05K1/113 , H05K2201/0323
Abstract: A circuit board structure includes a dielectric substrate, at least one embedded block, at least one electronic component, at least one first build-up circuit layer, and at least one second build-up circuit layer. The dielectric substrate includes a through cavity penetrating the dielectric substrate. The embedded block is fixed in the through cavity. The embedded block includes a first through hole and a second through hole. The electronic component is disposed in the through hole of the embedded block. The first build-up circuit layer is disposed on the top surface of the dielectric substrate and covers the embedded block. The second build-up circuit layer is disposed on the bottom surface of the dielectric substrate and covers the embedded block.
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公开(公告)号:US11665832B2
公开(公告)日:2023-05-30
申请号:US17234805
申请日:2021-04-20
Applicant: Unimicron Technology Corp.
Inventor: John Hon-Shing Lau , Cheng-Ta Ko , Pu-Ju Lin , Chi-Hai Kuo , Kai-Ming Yang , Chia-Yu Peng , Shao-Chien Lee , Tzyy-Jang Tseng
IPC: H05K1/00 , H05K1/02 , H05K1/03 , H05K1/09 , H05K1/11 , H05K1/14 , H05K1/16 , H05K1/18 , H05K3/20 , H05K3/36 , H05K3/38 , H05K3/40 , H05K3/46 , H05K3/02
CPC classification number: H05K3/46 , H05K3/022 , H05K3/386 , H05K3/4038
Abstract: A circuit board structure includes a first sub-board including a plurality of circuit patterns, a second sub-board including a plurality of pads, and a connecting structure layer having a plurality of through holes and including an insulating layer, first and second adhesive layers, and a plurality of conductive blocks. The first adhesive layer is directly connected to the first sub-board. The second adhesive layer is directly connected to the second sub-board. The through holes penetrate through the first adhesive layer, the insulating layer, and the second adhesive layer. The conductive blocks are located in the through holes. An upper surface and a lower surface of each conductive block are respectively lower than a first surface of the first adhesive layer and a second surface of the second adhesive layer relatively away from the insulating layer. Each circuit pattern contacts the upper surface, and each pad contacts the lower surface.
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公开(公告)号:US20230067112A1
公开(公告)日:2023-03-02
申请号:US17983396
申请日:2022-11-09
Applicant: Unimicron Technology Corp.
Inventor: Ra-Min Tain , John Hon-Shing Lau , Pu-Ju Lin , Wei-Ci Ye , Chi-Hai Kuo , Cheng-Ta Ko , Tzyy-Jang Tseng
Abstract: A vapor chamber structure includes a thermally conductive shell, a capillary structure layer, and a working fluid. The thermally conductive shell includes a first thermally conductive portion and a second thermally conductive portion. The first thermally conductive portion and the second thermally conductive portion are a thermally conductive plate that is integrally formed, and the thermally conductive shell is formed by folding the thermally conductive plate in half and then sealing the thermally conductive plate. The first thermally conductive portion has at least one first cavity, the second thermally conductive portion has at least one second cavity. At least one sealed chamber is defined between the thermally conductive plate, the first cavity and the second cavity. A pressure in the sealed chamber is lower than a standard atmospheric pressure. The capillary structure layer covers an inner wall of the sealed chamber. The working fluid is filled in the sealed chamber.
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公开(公告)号:US11540396B2
公开(公告)日:2022-12-27
申请号:US17191559
申请日:2021-03-03
Applicant: Unimicron Technology Corp.
Inventor: Tzyy-Jang Tseng , Shao-Chien Lee , John Hon-Shing Lau , Chen-Hua Cheng , Ra-Min Tain
IPC: H05K1/00 , H05K1/02 , H05K1/11 , H05K1/16 , H05K3/00 , H05K3/28 , H05K3/38 , H05K3/46 , H01L23/12 , H01L23/13 , H01L23/48 , H01L23/52 , H01L23/552 , H05K3/40 , H05K1/03
Abstract: A circuit board structure includes a first sub-circuit board, a second sub-circuit board, and a third sub-circuit board. The first sub-circuit board has an upper surface and a lower surface opposite to each other, and includes at least one first conductive through hole. The second sub-circuit board is disposed on the upper surface of the first sub-circuit board and includes at least one second conductive through hole. The third sub-circuit board is disposed on the lower surface of the first sub-circuit board and includes at least one third conductive through hole. At least two of the first conductive through hole, the second conductive through hole, and the third conductive through hole are alternately arranged in an axial direction perpendicular to an extending direction of the first sub-circuit board. The first sub-circuit board, the second sub-circuit board, and the third sub-circuit board are electrically connected to one another.
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公开(公告)号:US20220256717A1
公开(公告)日:2022-08-11
申请号:US17234805
申请日:2021-04-20
Applicant: Unimicron Technology Corp.
Inventor: John Hon-Shing Lau , Cheng-Ta Ko , Pu-Ju Lin , Chi-Hai Kuo , Kai-Ming Yang , Chia-Yu Peng , Shao-Chien Lee , Tzyy-Jang Tseng
Abstract: A circuit board structure includes a first sub-board including a plurality of circuit patterns, a second sub-board including a plurality of pads, and a connecting structure layer having a plurality of through holes and including an insulating layer, first and second adhesive layers, and a plurality of conductive blocks. The first adhesive layer is directly connected to the first sub-board. The second adhesive layer is directly connected to the second sub-board. The through holes penetrate through the first adhesive layer, the insulating layer, and the second adhesive layer. The conductive blocks are located in the through holes. An upper surface and a lower surface of each conductive block are respectively lower than a first surface of the first adhesive layer and a second surface of the second adhesive layer relatively away from the insulating layer. Each circuit pattern contacts the upper surface, and each pad contacts the lower surface.
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公开(公告)号:US20220231004A1
公开(公告)日:2022-07-21
申请号:US17714121
申请日:2022-04-05
Applicant: Unimicron Technology Corp.
Inventor: Ming-Ru Chen , Tzyy-Jang Tseng , Cheng-Chung Lo
Abstract: A manufacturing method of a light emitting diode (LED) package structure includes the following steps. A carrier is provided. A redistribution layer is formed on the carrier. A plurality of active devices are formed on the carrier. A plurality of LEDs are transferred on the redistribution layer. The LEDs and the active devices are respectively electrically connected to the redistribution layer. The active devices are adapted to drive the LEDs, respectively. A molding compound is formed on the redistribution layer to encapsulate the LEDs. The carrier is removed to expose a bottom surface of the redistribution layer.
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公开(公告)号:US20220126752A1
公开(公告)日:2022-04-28
申请号:US17123120
申请日:2020-12-16
Applicant: Unimicron Technology Corp.
Inventor: Tzyy-Jang Tseng , Shih-Yao Lin , Ansheng Lee , Meng-Chia Chan , Ming-Yuan Hsu , Chengming Weng
Abstract: A rear-view mirror with a display function includes a rear-view mirror body and a display structure layer. The display structure layer is disposed on one side of the rear-view mirror body and includes a plurality of light-emitting diodes and a driving circuit layer. The light-emitting diodes are located between the rear-view mirror body and the driving circuit layer. The light-emitting diodes are electrically connected to the driving circuit layer.
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公开(公告)号:US20220059498A1
公开(公告)日:2022-02-24
申请号:US17098436
申请日:2020-11-15
Applicant: Unimicron Technology Corp.
Inventor: Tzyy-Jang Tseng , Pu-Ju Lin , Cheng-Ta Ko , Ra-Min Tain
IPC: H01L25/065 , H01L23/538 , H01L23/00 , H01L23/498 , H01L23/48
Abstract: A chip package structure includes a substrate, a first chip, a second chip, a bridge, a plurality of first bumps, a plurality of second bumps, a plurality of third bumps and a plurality of solder balls. A first active surface of the first chip and a second active surface of the second chip face a first surface of the substrate. The bridge includes a high-molecular polymer layer and a pad layer located on the high-molecular polymer layer. The first chip is electrically connected to the substrate through the first bumps. The second chip is electrically connected to the substrate through the second bumps. The first chip and the second chip are electrically connected to the pad layer through the third bumps. The first bumps and the second bumps have the same size. The solder balls are disposed on a second surface of the substrate and electrically connected to the substrate.
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