中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

110 records (took 0.027 seconds)

    APPARATUS HAVING INNER LAYERS SUPPORTING SURFACE-MOUNT COMPONENTS
    83.
    发明授权
    APPARATUS HAVING INNER LAYERS SUPPORTING SURFACE-MOUNT COMPONENTS 失效
    VORRICHTUNG MITOBERFLÄCHENMONTIERTENBAUTEILEN TRAGENDEN INNENSCHICHTEN

    公开(公告)号：EP0749674B1

    公开(公告)日：1999-01-20

    申请号：EP95913541.9

    申请日：1995-03-09

    Applicant: THE PANDA PROJECT

    Inventor： CRANE, Stanford, W., Jr. ,  PORTUONDO, Maria, M.

    IPC: H05K3/34 ,  H05K3/40

    CPC classification number: H01L23/49861 ,  H01L23/49811 ,  H01L2924/0002 ,  H01L2924/181 ,  H05K1/112 ,  H05K3/308 ,  H05K3/321 ,  H05K3/3421 ,  H05K3/4623 ,  H05K2201/09472 ,  H05K2201/09536 ,  H05K2201/09645 ,  H05K2201/10189 ,  H05K2201/1031 ,  H05K2201/10318 ,  H05K2201/10704 ,  H05K2201/10772 ,  H05K2201/10893 ,  Y02P70/611 ,  Y02P70/613 ,  Y10T29/49126 ,  Y10T29/49147 ,  Y10T29/49149 ,  H01L2924/00 ,  H01L2924/00012

    Abstract: An apparatus comprising a multi-layer substrate (10) including a plurality of layers of insulative material (12), at least one well (15) formed in at least one of the layers, the well (15) extending from an outer surface of the multi-layer substrate to an inner surface of the multi-layer substrate, and an electrically conductive component (13) formed within the well (15) on the inner surface of the multi-layer substrate; and a device having at least one electrically conductive lead or wire (11) extending into the well (15) and being in direct physical contact with the electrically conductive component (13) formed on the inner surface of the multi-layer substrate. Also, a method of manufacturing an apparatus comprising the steps of forming a multi-layer substrate (10) including a plurality of layers of insulative material (12), at least one well (15) formed in at least one of the layers, the well (15) extending from an outer surface of the multi-layer substrate to an inner surface of the multi-layer substrate, and an electrically conductive component (13) formed within the well (15) on the inner surface of the multi-layer substrate; and extending at least one electrically conductive lead or wire (11) from a device into the well (15) such that the lead or wire is in direct physical contact with the electrically conductive component (13) formed on the inner surface of the multi-layer substrate.

    Abstract translation: 半导体管芯封装（30）包括多个导电引线（11）和用于承载电信号的多层结构（10），所述多层结构（10）包括多层绝缘材料（12a-12d） ），每个层包括在该层的相对侧上的第一表面和第二表面。 每个引线（11）延伸到完全延伸通过至少一个层的对应的阱（15），并且在一个层的一个表面上底部，阱（15）不通过该表面延伸并且电耦合 涉及形成在其对应的井（15）内的导电接合结构（13）。

    Interconnect structure
    86.
    发明公开
    Interconnect structure 审中-公开
    Verbindungsstruktur

    公开(公告)号：EP1643596A2

    公开(公告)日：2006-04-05

    申请号：EP05027017.2

    申请日：2001-09-17

    Applicant: NISSAN MOTOR CO., LTD.

    Inventor： Murakami, Yoshinori

    IPC: H01R12/04 ,  H05K3/36 ,  H05K7/14 ,  H01R24/00

    CPC classification number: H05K3/368 ,  H01L2224/48091 ,  H01L2224/49111 ,  H01L2924/13091 ,  H01R12/52 ,  H05K1/0216 ,  H05K1/145 ,  H05K1/148 ,  H05K1/162 ,  H05K3/36 ,  H05K2201/0792 ,  H05K2201/09672 ,  H05K2201/1028 ,  H05K2201/10818 ,  H05K2201/10893 ,  H01L2924/00014 ,  H01L2924/00

    Abstract: The invention related to an interconnect structure comprising a plurality of layered interconnects (1, 2, 3, 4) having mutually flush sides (41/51, 42/52, 43/53, 44/54), the plurality of layered interconnects (1, 2, 3, 4) each respectively comprising: a planer conductive body portion (1a, 2a), in a four-sided form having a pair of opposing sides (41/43, 42/44, 51/53, 52/54); and a pair of connecting portions (1A/1B, 2A/2B) respectively formed on the pair of opposing sides (41/43, 51/53). In such a structure, however, because there is a large partial inductance in the interconnection part, if an attempt is made to pass a large current, there is a possibility of signal delay and waveform deterioration occurring. Unless the optimum circuit interconnection placement is achieved within the circuitry of the lower-layer and the upper-layer circuit boards, the need could arise to achieve crossing of lines in a circuit board, thereby resulting in an increase in the size of the circuit boards or an increase in the impedance of the interconnections. Another problem with the structure of the past is a lack of protection against the induction of externally introduced noise, and faulty operation occurring when operating in a strong electromagnetic field. Additionally, there was the problem of electromagnetic noise generated from the interconnections. I order to solve the above-described problems the interconnect structure is characterized in that the plurality of layered interconnects (1, 2, 3, 4) are configured to have a reduced inductance.

    Abstract translation: 本发明涉及一种互连结构，其包括具有相互齐平的侧面（41/51,42 / 52,43 / 53,44 / 54）的多个分层互连（1,2,3,4），所述多个分层互连 1,2,3,4）分别包括：具有一对相对侧（41 / 43,42 / 44,51 / 53,52 / 52）的四边形式的平面导电体部分（1a，2a） 54）; 以及分别形成在所述一对相对侧（41/43,51 / 53）上的一对连接部分（1A / 1B,2A / 2B）。 然而，在这种结构中，由于在互连部分中存在大的部分电感，如果试图通过大电流，则存在发生信号延迟和波形劣化的可能性。 除非在下层电路板和上层电路板的电路内实现最佳电路互连布置，否则可能需要实现电路板中的线路交叉，从而导致电路板尺寸的增加 或互连的阻抗的增加。 过去结构的另一个问题是缺乏对外部引入噪声的感应的保护，以及在强电磁场中操作时发生的故障操作。 另外，存在从互连产生的电磁噪声的问题。 为了解决上述问题，为了解决上述问题，互连结构的特征在于，多个分层互连（1,2,3,4）被配置为具有减小的电感。

    Multilayer interconnection board and connection pin
    88.
    发明公开
    Multilayer interconnection board and connection pin 失效
    Mehrschichtige Leiterplatte und Verbindungsstift

    公开(公告)号：EP0899842A1

    公开(公告)日：1999-03-03

    申请号：EP98303249.1

    申请日：1998-04-27

    Applicant: Oki Electric Industry Co., Ltd.

    Inventor： Wada, Shigehito c/o Oki Electric Industry Co.,Ltd. ,  Saitou, Hisashi c/o Oki Electric Industry Co., Ltd ,  Morishima, Kazutoshi Oki System Tokyo Co., Ltd.

    IPC: H02B1/20 ,  H04Q1/14 ,  H01R9/28

    CPC classification number: H04Q1/145 ,  H01R9/28 ,  H04Q1/147 ,  H05K1/0286 ,  H05K3/4046 ,  H05K2201/09645 ,  H05K2201/10893

    Abstract: The interconnection board includes a plurality of non-conductive insulation layers and through-holes running through the insulation layers. A plurality of conductive patterns are provided on each insulation layer, electrically insulated from each other, and exposed to the inside of one through-hole at the same axial position of the through-hole. The connection pin has a non-conductive stem and a connection pattern provided on the non-conductive stem. The connection pattern extends in the axial direction of the connection pin and electrically connects two conductive patterns provided on different insulation layers at the same circumferential position in the through-hole, by bringing the conductive patterns into contact at positions which are axially different and circumferentially the same.

    Abstract translation: 互连板包括穿过绝缘层的多个非导电绝缘层和通孔。 多个导电图案设置在每个绝缘层上，彼此电绝缘，并且在通孔的相同轴向位置处暴露于一个通孔的内部。 连接销具有非导电杆和设置在非导电杆上的连接图案。 连接图案沿着连接销的轴向延伸，并且通过使导电图案在轴向不同并沿周向的位置接触地电连接设置在通孔中相同圆周位置处的不同绝缘层上的两个导电图案 相同。

    Printed circuit board having holes with multiple conductors
    90.
    发明公开
    Printed circuit board having holes with multiple conductors 失效
    Bedruckte Schaltplatte mitLöchernmit mehrfachen Leitern。

    公开(公告)号：EP0467698A2

    公开(公告)日：1992-01-22

    申请号：EP91306594.2

    申请日：1991-07-19

    Applicant: NORTHERN TELECOM LIMITED

    Inventor： Barnhouse, Robert L. ,  Estes, H. Scott

    IPC: H05K3/42

    CPC classification number: H05K3/403 ,  H05K3/0047 ,  H05K3/043 ,  H05K3/061 ,  H05K3/108 ,  H05K3/308 ,  H05K3/427 ,  H05K2201/09181 ,  H05K2201/09645 ,  H05K2201/10295 ,  H05K2201/10893 ,  H05K2203/0557

    Abstract: A printed circuit board having holes provided with two or more electrical conductors (16,34) on the surface of each hole. The conductors are circumferentially spaced apart around each hole so as to electrically isolate them from one another and each conductor is connected to an individual circuit line of the board. The conductors may be through-hole conductors. Alternatively, the holes are pin receiving holes for insertion of pins having two or more conductor lines for electrical contact with the conductors within the holes.

    Abstract translation: 一种印刷电路板，具有在每个孔的表面上设置有两个或多个电导体（16,34）的孔。 导体围绕每个孔周向间隔开，以便将它们彼此电隔离，并且每个导体连接到板的单独电路线。 导体可以是通孔导体。 或者，孔是用于插入具有两个或更多个导线的销的销接收孔，用于与孔内的导体电接触。

Patent Agency Ranking