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公开(公告)号：KR1020140020118A
公开(公告)日：2014-02-18
申请号：KR1020120086757
申请日：2012-08-08
Applicant: 삼성전기주식회사
CPC classification number: H01F17/0013 , H01F27/006 , H01F27/33 , H01F2017/002 , H01F2017/0093
Abstract: In the present invention, disclosed is a filter for removing a noise, which includes: a bottom coil layer around which a first bottom coil and a second bottom coil are wound in parallel; a top coil layer around which a second top coil arranged on the upper side of the first bottom coil and a first top coil arranged on the upper side of the second bottom coil are wound in parallel; and a first via and a second via which are interposed between the bottom coil layer and the top coil layer and alternatively, continuously, and electrically connect the first bottom coil, the first top coil, the second bottom coil, and the second top coil to the top coil layer and the bottom coil layer at single winding, respectively. According to the present invention, high common mode impedance is implemented in the same frequency and performance and capacity are improved. Productivity is improved and manufacturing costs are reduced by simplifying a structure and manufacturing processes.
Abstract translation: 在本发明中，公开了一种去除噪声的滤波器，其包括：底部线圈层，第一底部线圈和第二底部线圈平行地卷绕在底部线圈层上; 绕着第一底部线圈的上侧设置的第二顶部线圈和布置在第二底部线圈的上侧的第一顶部线圈并列缠绕的顶部线圈层; 以及插入在所述底部线圈层和所述顶部线圈层之间的第一通孔和第二通孔，或者，连续地并且将所述第一底部线圈，所述第一顶部线圈，所述第二底部线圈和所述第二顶部线圈电连接到 分别是单绕组的顶部线圈层和底部线圈层。 根据本发明，在相同频率下实现高共模阻抗，并提高性能和容量。 通过简化结构和制造工艺，提高了生产率并降低了制造成本。
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公开(公告)号：KR101141352B1
公开(公告)日：2012-05-03
申请号：KR1020100002879
申请日：2010-01-12
Applicant: 삼성전기주식회사
IPC: H01G11/12
CPC classification number: H01G9/155 , H01G9/016 , H01G9/08 , H01G11/28 , H01G11/52 , H01G11/74 , H01G11/82 , H01G11/84 , Y02E60/13 , Y02T10/7022 , Y10T29/417
Abstract: 본 발명은 전기 이중층 커패시터 및 그 제조방법에 관한 것으로서, 본 발명의 일 실시 형태에 따른 전기 이중층 커패시터는 내부에 수납공간을 가지며 절연성 수지로 이루어진 외장 케이스; 상기 외장 케이스에 매립되며, 상기 수납공간으로 노출되는 제1면과 상기 외장 케이스의 외부영역으로 노출되는 제2면을 각각 갖는 제1 및 제2 외부 단자; 및 상기 수납공간에 배치되며, 상기 제1면과 전기적으로 연결된 칩형 전기 이중층 커패시터 셀;을 포함하고, 상기 칩형 전기 이중층 커패시터 셀은 서로 대향 배치되며, 서로 반대 극성의 전기가 인가되는 제1 및 제2 전극, 상기 제1 및 제2 전극 사이에 배치되며, 전기가 인가되지 않는 적어도 하나 이상의 유도 전극층, 및 상기 제1 및 제2 전극과 상기 유도 전극층 사이에 각각 배치된 제1 및 제2 분리막을 포함한다.
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公开(公告)号：KR1020110082932A
公开(公告)日：2011-07-20
申请号：KR1020100002879
申请日：2010-01-12
Applicant: 삼성전기주식회사
IPC: H01G11/12
CPC classification number: H01G9/155 , H01G9/016 , H01G9/08 , H01G11/28 , H01G11/52 , H01G11/74 , H01G11/82 , H01G11/84 , Y02E60/13 , Y02T10/7022 , Y10T29/417
Abstract: PURPOSE: An electric double layer capacitor is provided to forms an external case and an external terminal into one body, thereby making better use of a space and minimizing the electric double layer capacitor and having the high energy storage density. CONSTITUTION: An external case has a storage space upon inside and is comprised of insulating resins. First and second external terminals(130a,130b) are buried to the external case and have the first side exposed to the storage space and the second side exposed to an external domain of the case. A chip type electric double layer capacitor cell is arranged in the storage space and electrically connected to the first side. The first and second separation films(124a,124b) arrange the chip type electric double layer capacitor cell to face each other and are arranged among the first electrode, the second electrode and induction electrode layer.
Abstract translation: 目的：提供双电层电容器，以形成一个外壳和一个外部端子成为一体，从而更好地利用空间并最小化双电层电容器并具有高能量存储密度。 构成：外壳在内部有一个储存空间，由绝缘树脂组成。 第一和第二外部端子（130a，130b）被埋入到外部壳体中，并且第一侧面暴露于存储空间，而第二侧面暴露于壳体的外部区域。 芯片型双电层电容器电池布置在存储空间中并与第一侧电连接。 第一和第二分离膜（124a，124b）将芯片型双电层电容器单元彼此面对布置在第一电极，第二电极和感应电极层之间。
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公开(公告)号：KR100809221B1
公开(公告)日：2008-02-29
申请号：KR1020070010088
申请日：2007-01-31
Applicant: 삼성전기주식회사
IPC: H01L33/02 , H01L21/205
Abstract: A method for fabricating a nitride semiconductor light emitting device using surfactant is provided to obtain a p-type nitride semiconductor layer with an excellent layer quality and an increased hole density by supplying surfactant of at least one of Sb, Bi, As, P, Ti, Se, Te, Po, Ge, Sn and Pb when or right before a p-type nitride semiconductor layer is grown. In a period of time to stop temporarily the growth process between a process of growing an active layer and a process of growing a p-type nitride semiconductor layer, in a period of time to grow a p-type nitride semiconductor layer or in a period of time to stop temporarily the growth process during a process of growing the p-type nitride semiconductor layer, surfactant including at least one of Sb, Bi, As, P, Ti, Se, Te, Po, Ge, Sn and Pb is supplied to a reactor to be absorbed to the surface of a nitride semiconductor(S2). The surfactant can be supplied as a source of a gas state to the inside of the reactor.
Abstract translation: 提供一种使用表面活性剂制造氮化物半导体发光器件的方法，通过提供Sb，Bi，As，P，Ti中的至少一种的表面活性剂来获得具有优异的层质量和增加的空穴密度的p型氮化物半导体层 ，Se，Te，Po，Ge，Sn和Pb，或者在p型氮化物半导体层生长之前。 在一段时间内暂时停止生长活性层的过程和生长p型氮化物半导体层的过程之间的生长过程，在生长p型氮化物半导体层的时间段内或在时间段 的时间，以在生长p型氮化物半导体层的过程中暂时停止生长过程，提供包括Sb，Bi，As，P，Ti，Se，Te，Po，Ge，Sn和Pb中的至少一种的表面活性剂 到要被吸收到氮化物半导体的表面的反应器（S2）。 可以将表面活性剂作为气体状态的源供应到反应器的内部。
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Patent Agency Ranking
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公开(公告)号：KR1020100073879A
公开(公告)日：2010-07-01
申请号：KR1020080132664
申请日：2008-12-23
Applicant: 삼성전기주식회사 , 한양대학교 산학협력단
CPC classification number: G06F17/5036
Abstract: PURPOSE: A modeling circuit and a modeling method thereof are provided to accurately model a high frequency device by separately modeling the overlapped region and the non-overlapped region of a high frequency device. CONSTITUTION: A first circuit part(310) is formed by modeling the overlapped region of a high frequency device according to the coupled transmission line theory. The first circuit part comprises a first capacitor and a first conductor. A second circuit part(320) is formed by modeling the non-overlapping region of a high frequency device according to a series RL model. A second circuit part comprises a first inductor and a first resistor. A first and a second circuit part form a primary self-resonant frequency of a high frequency device.
Abstract translation: 目的：提供一种建模电路及其建模方法，通过对高频设备的重叠区域和非重叠区域进行单独建模，对高频设备进行精确建模。 构成：根据耦合传输线理论，通过对高频器件的重叠区域进行建模来形成第一电路部分（310）。 第一电路部分包括第一电容器和第一导体。 通过根据RL系列模型对高频装置的非重叠区域进行建模来形成第二电路部分（320）。 第二电路部分包括第一电感器和第一电阻器。 第一和第二电路部分形成高频器件的初级自谐振频率。
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