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公开(公告)号：KR101711193B1
公开(公告)日：2017-02-28
申请号：KR1020100053035
申请日：2010-06-04
Applicant: 삼성전자주식회사
IPC: H01L21/66
CPC classification number: G01N23/2251 , G01N21/9501 , G01N21/95607 , G06T7/001 , G06T2207/30148
Abstract: 포토맵 정보에기초하여웨이퍼검사를수행하는웨이퍼검사가개시된다. 웨이퍼검사방법은, 웨이퍼상의샘플센터로케이션(sample center location)을검출하는단계, 포토맵 정보에기초하여검출된샘플센터로케이션을보정센터로케이션으로보정하는단계, 및보정센터로케이션에기초하여웨이퍼에포함된결함다이들을검출하는단계를포함한다.
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公开(公告)号：KR1020110133357A
公开(公告)日：2011-12-12
申请号：KR1020100053035
申请日：2010-06-04
Applicant: 삼성전자주식회사
IPC: H01L21/66
CPC classification number: G01N23/2251 , G01N21/9501 , G01N21/95607 , G06T7/001 , G06T2207/30148
Abstract: PURPOSE: A wafer inspecting method and a wafer inspecting system are provided to inspect a wafer based on photo map information, thereby increasing defect analyzing efficiency. CONSTITUTION: A sample center location on a wafer is detected(S101). The detected sample center location is corrected into a correction center location based on the photo map information(S103). The photo map information includes a wafer die pitch and offset information. Defective dies included in the wafer are detected based on the correction center location(S105).
Abstract translation: 目的：提供晶片检查方法和晶片检查系统，以根据照片地图信息检查晶片，从而提高缺陷分析效率。 构成：检测晶片上的样品中心位置（S101）。 基于照片地图信息将检测到的样本中心位置校正到校正中心位置（S103）。 照片地图信息包括晶片模间距和偏移信息。 基于校正中心位置来检测包含在晶片中的有缺陷的管芯（S105）。
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公开(公告)号：KR1019940005732B1
公开(公告)日：1994-06-23
申请号：KR1019910014340
申请日：1991-08-20
Applicant: 삼성전자주식회사
Inventor： 고장만
IPC: H01L29/70
Abstract: The method forms an emitter electrode and emitter junction by poly-silicon, and forms an emitter layer of low density around an emitter layer of high density by a self-alignment array. The method prolongs a life time of device, reduces a serial resistance of base, and increases an insulation voltage between emitter and base. The method includes a process which inserts B ion, a process which forms a purity base area (51), a process which inserts As ion, a process which etches a nitrogen layer (7), a 2nd thermal oxidation layer (6) and a 1st poly silicon layer (5), a process which forms an emitter, a process which inserts B ion, and a process which forms a high density emitter (53), low density emitter (54) and purity base layer (51).
Abstract translation: 该方法通过多晶硅形成发射极和发射极结，并且通过自对准阵列在高密度的发射极层周围形成低密度的发射极层。 该方法延长了器件的使用寿命，降低了基极的串联电阻，并增加了发射极与基极之间的绝缘电压。 该方法包括插入B离子的方法，形成纯碱性面积（51）的方法，插入As离子，蚀刻氮层（7），第二热氧化层（6）和 第一多晶硅层（5），形成发射极的工艺，插入B离子的工艺以及形成高密度发射极（53），低密度发射极（54）和纯碱性层（51）的工艺。
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Patent Agency Ranking
公开(公告)号：KR1019930000295B1
公开(公告)日：1993-01-15
申请号：KR1019890008006
申请日：1989-06-10
Applicant: 삼성전자주식회사
Inventor： 고장만
Abstract: The method for forming a lateral diffusion layer by using a self- aligning method to integrate an NPN transistor and a lateral PNP transistor simultaneously comprises forming a buried layer (2), an N epitaxial layer (3), a P device isolation region (5) and an N collector layer (4) onto a P substrate (1), forming a field oxide film (6) thereon, forming a pad oxide film (7) to implant P impurities to form an intrinsic base region (12a), forming an emiter and collector region (12b) of the NPN TR., forming a link base region (21c), depositing a poly silicon (15) thereon the implant N impurities to diffuse the implanted impurities to deposit an metallic layer (17) thereon, etching the layrs (15,17) to define an emiter region to deposit an oxide film (16) and forming metallic wirings (20-23).
Abstract translation: 通过使用自对准方法来同时集成NPN晶体管和横向PNP晶体管的横向扩散层的形成方法同时包括形成掩埋层（2），N外延层（3），P器件隔离区（5） ）和N个集电极层（4）放置到P基板（1）上，在其上形成场氧化膜（6），形成衬垫氧化膜（7）以注入P杂质以形成本征基极区域（12a），形成 形成连接基区域（21c），在其上沉积植入物N杂质上的多晶硅（15）以扩散注入的杂质以在其上沉积金属层（17），所述NPN TR的放电器和集电极区域（12b） 蚀刻铺层（15,17）以限定沉积氧化膜（16）并形成金属配线（20-23）的电晕区域。
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公开(公告)号：KR1020000067291A
公开(公告)日：2000-11-15
申请号：KR1019990014979
申请日：1999-04-27
Applicant: 삼성전자주식회사
IPC: H01L21/78
Abstract: PURPOSE: A scribe line is provided to prevent a mechanical stress generated by sawing from transmitting into a main chip to obtain a stable operative property of the main chip. CONSTITUTION: A scribe line comprises an insulating substrate(10), a first interlevel insulating film(12a) formed on the substrate(10) and having a plural of first through holes to allow the substrate to be exposed in part, a first stress stopping pattern(s1) formed the internal of the first through holes and taking a conductive plug shape, a second interlevel insulating film(12b) formed on the resulting product and having a plural of second through holes to allow the first stress stopping pattern to be exposed in part, a second stress stopping pattern(s2) formed the internal of the second through holes and taking a conductive plug shape, a third interlevel insulating film(12c) formed on the resulting product and having a plural of third through holes to allow the second stress stopping pattern(s2) to be exposed in part, a third stress stopping pattern(s3) formed on the third interlevel insulating film(12c) including the second through holes and having a laminated structure of conductive plug/conductive film pattern,
Abstract translation: 目的：提供划线，以防止锯切产生的机械应力传输到主芯片，以获得主芯片的稳定操作性能。 构成：划线包括绝缘基板（10），形成在基板（10）上的第一层间绝缘膜（12a），并且具有多个第一通孔以允许基板部分露出，第一应力停止 图案（s1）形成第一通孔的内部并且具有导电塞形状，形成在所得产品上的第二层间绝缘膜（12b），并具有多个第二通孔，以允许第一应力停止图案露出 部分地形成有形成在第二通孔的内部并且具有导电塞形状的第二应力停止图案（s2），形成在所得产品上的具有多个第三通孔的第三层间绝缘膜（12c），以允许 形成在包括第二通孔的第三层间绝缘膜（12c）上形成的具有导体层叠结构的第三应力停止图案（s3）的第二应力停止图案（s2） ve插头/导电膜图案，
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公开(公告)号：KR100149345B1
公开(公告)日：1998-10-01
申请号：KR1019940031899
申请日：1994-11-30
Applicant: 삼성전자주식회사
Inventor： 고장만
IPC: H01L27/108
Abstract: 본 발명은 반도체장치로 구성되는 커패시터의 제조방법으로서 하부전극으로 텅스텐 실리사이드를 사용하고 절연물로 질화막 또는 질화막과 얇은 산화막의 이중구조로 형성할 때 하부전극인 텅스텐 실리사이드층 위에 자연적으로 생성되는 산화막의 상태가 고르지 않아 커패시턴스 값의 산포가 일정하지 않게 되어 디바이스의 신뢰성이 문제가 되는 점을 개선하기 위하여 텅스텐 실리사이드층 위에 얇은 폴리실리콘을 침적시키는 공정을 추가함으로서 신터링 공정을 진행할 때 도프되지 않은 얇은 폴리실리콘이 충분히 도핑되어 하부전극으로 함께 사용되어 균일한 커패시턴스 값을 갖게하는 커패시터의 제조방법을 제공한다.
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