公开(公告)号：KR102251363B1

公开(公告)日：2021-05-14

申请号：KR1020140102418

申请日：2014-08-08

Applicant: 삼성전자주식회사

Inventor： 김철 ,  김동현 ,  김명철 ,  김대용 ,  김철성

IPC: H01L29/78 ,  H01L21/336

Abstract: 반도체소자및 이를제조하는방법을제공한다. 반도체소자는, 기판상에배치된핀형액티브패턴들과게이트전극들, 게이트전극양측벽에배치되는제1 스페이서및 제2 스페이서, 게이트전극양측에배치되는제1 및제2 불순물영역들, 제1 불순물영역과전기적으로연결되는콘택플러그및 콘택플러그를감싸며, 콘택플러그의상부면과동일한높이에상부면을갖는제3 스페이서를포함한다.

公开(公告)号：KR1020170035310A

公开(公告)日：2017-03-30

申请号：KR1020150181279

申请日：2015-12-17

Applicant: 삼성전자주식회사

Inventor： 양준혁 ,  김대용 ,  김상호 ,  박재진

IPC: G05F1/56 ,  H03F1/22 ,  H03K17/687

Abstract: 멀티-파워와게인부스팅기술을이용하는전압레귤레이터가공개된다. 상기전압레귤레이터는제1노드로공급되는제1전압을동작전압으로서사용하고, 기준전압과네거티브피드백루프를통해수신되는피드백전압과의차이를증폭하고증폭된전압을출력하는에러증폭기와, 제2전압을공급하는제2노드와상기전압증폭기의출력노드사이에연결된전력트랜지스터와, 상기제1전압의제1파워시퀀스, 상기제2전압의제2파워시퀀스, 및동작제어신호에기초하여, 상기전력트랜지스터의게이트로공급되는게이트전압의레벨과상기전력트랜지스터의바디로공급되는바디전압의레벨을선택하는스위치회로를포함한다.

Abstract translation: 公开了一种使用多功率和增益增强技术的电压调节器。 以及使用所述电压调节器的第一电压误差放大器被提供到第一节点作为操作电压，并放大所述反馈电压之间的差是通过参考电压和负反馈回路和输出放大后的电压，所述第二接收 和连接在第二节点和提供电压功率晶体管，所述第二功率序列的基础上，所述电压放大器的输出节点，并且第一电压的操作控制信号的第二电压的第一功率序列，其中间 以及开关电路，用于选择提供给功率晶体管的栅极的栅极电压的电平和提供给功率晶体管的本体的本体电压的电平。

公开(公告)号：KR101602251B1

公开(公告)日：2016-03-11

申请号：KR1020090098742

申请日：2009-10-16

Applicant: 삼성전자주식회사

Inventor： 이은옥 ,  김대용 ,  최길현 ,  김병희

IPC: H01L21/28

CPC classification number: H01L29/66621 ,  H01L21/76831 ,  H01L21/76885 ,  H01L21/76889 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10894 ,  H01L29/4236 ,  H01L29/665 ,  H01L29/78

Abstract: 배선구조물및 이의형성방법에서, 상기배선구조물은, 기판상에콘택홀을포함하는절연막이구비된다. 상기콘택홀을채우는제1 콘택플러그및 상기절연막상부면으로돌출되는도전성라인이일체로이루어지고, 상기도전성라인표면의적어도일부분은금속실리사이드를포함하는제1 배선을포함한다. 상기제1 배선사이의갭을매립하는층간절연막이구비된다. 또한, 상기층간절연막및 상기절연막을관통하는제2 콘택플러그가구비된다. 상기배선구조물은금속실리사이드를포함하므로낮은저항을갖는다.

公开(公告)号：KR1020150068541A

公开(公告)日：2015-06-22

申请号：KR1020130153985

申请日：2013-12-11

Applicant: 삼성전자주식회사

Inventor： 유성민 ,  김대용 ,  김주화

IPC: G11C5/14

CPC classification number: G11C5/147 ,  G11C5/148 ,  H02M3/158

Abstract: 본발명의메모리컨트롤러는, 슬립모드에서턴오프되고, 액티브모드에서턴온되는액티브레귤레이터, 상기액티브레귤레이터로부터생성된구동전압을제공받는액티브로직, 상기액티브레귤레이터의출력단과상기액티브로직의전원입력단을연결또는차단하되, 상기액티브모드가시작된후 과도상태구간이경과된후에턴온되는파워게이팅스위치, 그리고상기과도상태구간동안상기액티브로직의전원입력단을충전하여승압시키는충전회로를포함한다.

Abstract translation: 根据本发明的存储器控​​制器包括一个主动调节器，其以滑动模式被关断并且在一个激活模式下导通;一个有源逻辑，其接收从该有源调节器产生的驱动电压;一个电源门控开关，其连接或 断开有源稳压器的输出端和有源逻辑的电源输入端，并且在激活模式启动之后经过瞬态状态部分之后导通;以及充电电路，其通过对有源模式的电源输入端充电来提升电压 瞬态状态部分的逻辑。

公开(公告)号：KR1020130131755A

公开(公告)日：2013-12-04

申请号：KR1020120055543

申请日：2012-05-24

Applicant: 삼성전자주식회사

Inventor： 신충환 ,  강상범 ,  김대용 ,  김정익 ,  김철성 ,  류제형 ,  이상우 ,  최효석

IPC: H01L21/28

CPC classification number: H01L29/7839 ,  H01L21/26506 ,  H01L21/28 ,  H01L21/28518 ,  H01L21/28537 ,  H01L21/76814 ,  H01L23/485 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/401 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/66643 ,  H01L29/78 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are a semiconductor device comprising metal silicide and a manufacturing method thereof. The semiconductor device comprises a gate formed on a substrate; an elevated source/drain formed in both sides of the gate; and the metal silicide formed on a part of the elevated source/drain.. The elevate source/drain is protruded from the surface of the substrate and comprises a protrusion unit which surrounds the both sides of the metal silicide.

Abstract translation: 提供一种包含金属硅化物的半导体器件及其制造方法。 半导体器件包括形成在衬底上的栅极; 在门的两侧形成升高的源极/漏极; 以及形成在升高的源极/漏极的一部分上的金属硅化物。提升的源极/漏极从衬底的表面突出并且包括围绕金属硅化物的两侧的突出单元。

公开(公告)号：KR1020080049163A

公开(公告)日：2008-06-04

申请号：KR1020060119422

申请日：2006-11-30

Applicant: 삼성전자주식회사

Inventor： 이은옥 ,  김현수 ,  김대용 ,  정은지 ,  최길현 ,  김병희 ,  윤종호

IPC: H01L21/28 ,  H01L21/3205

CPC classification number: H01L21/76877 ,  H01L21/7684 ,  H01L21/76864 ,  H01L21/76871

Abstract: A method for forming a conductive layer and a method for forming a contact and a wiring by using the same are provided to enhance reliability and productivity by forming a tungsten layer on a cobalt layer as an underlayer. An interlayer dielectric(108) is formed on an upper surface of a semiconductor substrate(100). A contact hole(110) for exposing a part of the semiconductor substrate is formed by etching the interlayer dielectric. A cobalt layer is formed on an inner surface of the contact hole and a surface of the interlayer dielectric. A tungsten layer for filling up the inside of the contact hole is formed on the cobalt layer by using the cobalt layer as a seed. A contact is formed by polishing the tungsten layer and the cobalt layer in order to expose the interlayer dielectric.

Abstract translation: 提供形成导电层的方法以及通过使用该方法形成接触和布线的方法，以通过在作为底层的钴层上形成钨层来提高可靠性和生产率。 在半导体衬底（100）的上表面上形成层间电介质（108）。 通过蚀刻层间电介质形成用于暴露半导体衬底的一部分的接触孔（110）。 在接触孔的内表面和层间电介质的表面上形成钴层。 通过使用钴层作为种子，在钴层上形成用于填充接触孔内部的钨层。 通过抛光钨层和钴层来形成接触，以暴露层间电介质。

公开(公告)号：KR1020080044455A

公开(公告)日：2008-05-21

申请号：KR1020060113344

申请日：2006-11-16

Applicant: 삼성전자주식회사

Inventor： 김현수 ,  이은옥 ,  김대용 ,  정은지 ,  최길현 ,  김병희 ,  윤종호

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66628 ,  H01L21/76224

Abstract: A semiconductor device and a method for forming the same are provided to previously suppress a bridge phenomenon between active regions and disconnection between contacts. A semiconductor device includes device isolation patterns(110), a gate insulation layer, a gate electrode, spacers, and source/drain regions. The device isolation patterns define an active region(112). The gate insulation layer is arranged on a channel region of the active region. The gate electrode is arranged on the gate insulation layer. The spacers are formed at both sidewalls of the gate electrode. The source/drain regions are arranged between the spacers and device isolation patterns, and an upper surface higher than a surface of the active region. The substrate and the source/drain regions include single crystal silicon or single crystal silicon germanium.

Abstract translation: 提供半导体器件及其形成方法，以预先抑制有源区域之间的桥接现象和触点之间的断开。 半导体器件包括器件隔离图案（110），栅极绝缘层，栅极电极，间隔物和源极/漏极区域。 设备隔离模式定义活动区域（112）。 栅绝缘层布置在有源区的沟道区上。 栅极布置在栅极绝缘层上。 间隔物形成在栅电极的两个侧壁处。 源极/漏极区域布置在间隔物和器件隔离图案之间，以及高于活性区域的表面的上表面。 衬底和源/漏区包括单晶硅或单晶硅锗。

公开(公告)号：KR1020080008766A

公开(公告)日：2008-01-24

申请号：KR1020060068458

申请日：2006-07-21

Applicant: 삼성전자주식회사

Inventor： 정은지 ,  윤종호 ,  김대용 ,  김현수 ,  김병희 ,  이은옥

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L21/28097 ,  H01L29/4975 ,  H01L29/66545 ,  H01L21/82345

Abstract: A method for manufacturing a semiconductor device is provided to enhance the electric reliability of the semiconductor device by implementing fully silicided gate patterns with different thicknesses from one another on a semiconductor substrate. A thin layer(32) with silicon is formed on a substrate. By executing an electroless plating, a transition metal layer(38) is formed on the thin layer. By executing a thermal treatment, the thin layer is reacted with the transition metal layer and then the thin layer and the transition metal layer are formed as a silicide layer.

Abstract translation: 提供了一种用于制造半导体器件的方法，以通过在半导体衬底上实现彼此具有不同厚度的完全硅化栅极图案来增强半导体器件的电可靠性。 在衬底上形成具有硅的薄层（32）。 通过执行化学镀，在薄层上形成过渡金属层（38）。 通过进行热处理，使薄层与过渡金属层反应，然后将薄层和过渡金属层形成为硅化物层。

公开(公告)号：KR1020080006807A

公开(公告)日：2008-01-17

申请号：KR1020060066000

申请日：2006-07-13

Applicant: 삼성전자주식회사

Inventor： 정은지 ,  윤종호 ,  김대용 ,  김현수 ,  김병희 ,  이은옥

IPC: H01L21/24 ,  H01L21/336

Abstract: A semiconductor device having a salicide layer and a method for fabricating the same are provided to lower the electrical resistance of a wiring by patching a disconnected part of the salicide layer with a metal or a metal silicide. An active region(51) is defined on a semiconductor substrate. A gate electrode crosses an upper surface of the active region. A plurality of spacer patterns(54) are formed on both sidewalls of the gate electrode. A gate salicide layer(56g) is formed on an upper surface of the gate electrode and is partially disconnected. Source/drain salicide layers(56s,56d) are formed on the active region of both sides of the gate electrode. A conductive patch layer(60) is formed on the gate electrode of the disconnected part of the gate salicide layer. The conductive patch layer is plated by using an electroless-plating method. The conductive patch layer is electrically connected to the gate salicide layer.

Abstract translation: 提供一种具有自对准硅化物层的半导体器件及其制造方法，通过用金属或金属硅化物修补隔离部分的自对准硅化物层来降低布线的电阻。 有源区（51）被限定在半导体衬底上。 栅电极与有源区的上表面交叉。 多个间隔物图案（54）形成在栅电极的两个侧壁上。 栅极自对准层（56g）形成在栅电极的上表面上并且部分地断开。 在栅极两侧的有源区上形成源极/漏极自对准硅化物层（56s，56d）。 在栅极自对准硅化物层的断开部分的栅电极上形成导电贴片层（60）。 通过使用无电镀方法对导电贴片层进行电镀。 导电贴片层电连接到栅极化硅化物层。

公开(公告)号：KR1020070098312A

公开(公告)日：2007-10-05

申请号：KR1020060029815

申请日：2006-03-31

Applicant: 삼성전자주식회사

Inventor： 김대용

IPC: H02H9/04

CPC classification number: H03K17/6877 ,  H03K17/0822 ,  H03K17/223 ,  H03K17/302

Abstract: An overvoltage protection method and an overvoltage protection circuit are provided to reduce a chip layout size by arranging an overvoltage detecting logic inside an IC chip. An overvoltage protection circuit includes a voltage converter(120), a voltage comparator(160), and a switching unit(140). The voltage converter converts a source voltage to first and second voltages. The voltage comparator compares the first voltage with the second voltage and generates a control signal. The switching unit determines whether the source voltage is to be applied on a chip based on the control signal. The voltage converter is arranged inside the chip. The voltage converter includes a first and second voltage generators. The first voltage generator converts the source voltage to the first voltage, while the second voltage generator converts the source voltage to the second voltage.

Abstract translation: 提供过压保护方法和过电压保护电路，通过在IC芯片内布置过电压检测逻辑来减小芯片布局尺寸。 过压保护电路包括电压转换器（120），电压比较器（160）和开关单元（140）。 电压转换器将源电压转换为第一和第二电压。 电压比较器将第一电压与第二电压进行比较，并产生控制信号。 开关单元基于控制信号确定是否将源电压施加在芯片上。 电压转换器布置在芯片内部。 电压转换器包括第一和第二电压发生器。 第一电压发生器将源电压转换为第一电压，而第二电压发生器将源电压转换为第二电压。