-
公开(公告)号：KR1019990012397A
公开(公告)日：1999-02-25
申请号：KR1019970035771
申请日：1997-07-29
Applicant: 삼성전자주식회사
IPC: G11C11/40
Abstract: 본 발명은 내부전압회로를 구비하는 반도체장치의 회로에 관해 개시한다. 본 발명은 내부전압회로 출력단에 PMOS트랜지스터와 전압 검출기로 구성되는 내부 인가 전압 조절 수단이 연결되어 외부인가 전압 초기에는 상기 내부 인가 조절 수단에 의해 내부 전압이 인가되고 그 이후에는 상기 내부전압회로에 의해 내부 전압이 인가된다. 이렇게 함으로써 상기 내부전압회로에서 바이폴라 접합 트랜지스터의 베이스와 이미터간의 전압강하에 의해 내부 인가 전압이 감소되는 것을 방지할 수 있다. 따라서 상기 외부인가 전압의 인가와 동시에 상기 내부인가 전압이 나타나게 하여 반도체장치의 저 전력 특성이 취약해지는 것을 방지함과 아울러 반도체장치의 고속화도 보장할 수 있다.
-
公开(公告)号：KR1020020030899A
公开(公告)日：2002-04-26
申请号：KR1020000061257
申请日：2000-10-18
Applicant: 삼성전자주식회사
IPC: G11C29/00
CPC classification number: G11C17/16
Abstract: PURPOSE: A fuse circuit of semiconductor memory device is provided to reduce badness generation probability though a fuse cutting is not accurately. CONSTITUTION: A fuse circuit comprises a plurality of fuses(101,102) and a plurality of transmission gates(111,112). The transmission gates(111,112) have input terminals(IN1,IN2) and output terminals(OUT1,OUT2), and are connected in series between a power supply voltage(VDD) or an input signal and an output terminal(D). The fuse(101) whose one end is connected to the power supply voltage(VDD) has the other end connected to a resistor(131). The fuse(102) whose one end is connected to the power supply voltage(VDD) has the other end connected to a resistor(132). The transmission gate(111) operates in response to a logic state of the other end of the fuse(101) and its inverted state via an inverter(121). The transmission gate(112) operates in response to a logic state of the other end of the fuse(102) and its inverted state via an inverter(122).
Abstract translation: 目的：提供一种半导体存储器件的熔丝电路，以便通过熔丝切割不准确来减少不良发生的概率。 构成：熔丝电路包括多个保险丝（101,102）和多个传输门（111,112）。 传输门（111,112）具有输入端（IN1，IN2）和输出端（OUT1，OUT2），并串联连接在电源电压（VDD）或输入信号与输出端（D）之间。 其一端与电源电压（VDD）连接的保险丝（101）的另一端与电阻（131）连接。 其一端连接到电源电压（VDD）的保险丝（102）的另一端连接到电阻（132）。 传输门（111）响应于熔丝（101）的另一端的逻辑状态和经由反相器（121）的反相状态而工作。 传输门（112）经由反相器（122）响应于熔丝（102）的另一端的逻辑状态及其反相状态而工作。
-
公开(公告)号：KR100487530B1
公开(公告)日：2005-05-03
申请号：KR1020020044225
申请日：2002-07-26
Applicant: 삼성전자주식회사
IPC: H01L21/66
CPC classification number: G01R31/2884
Abstract: 테스트 소자 그룹이 구비된 반도체 소자를 제공한다. 이 소자는 반도체 기판 상에 형성된 복수개의 칩 영역들과 칩 영역들을 분할하는 스크라이브 영역(scribe region)을 포함한다. 칩 영역 내에 복수개의 메인 패드들이 배치되고, 스크라이브 영역에 테스트 소자 그룹(TEG;Test Element Group)들이 배치된다. 테스트 소자 그룹과 소정의 메인 패드들은 배선을 통하여 전기적으로 연결된다.
-
公开(公告)号：KR1020040009866A
公开(公告)日：2004-01-31
申请号：KR1020020044225
申请日：2002-07-26
Applicant: 삼성전자주식회사
IPC: H01L21/66
CPC classification number: G01R31/2884
Abstract: PURPOSE: A semiconductor device including a test element group is provided to increase the number of chips formed on a wafer and enhance the productivity by reducing the width of a scribe region between main chips. CONSTITUTION: A semiconductor device including a test element group includes a plurality of chip regions(22), a scribe region(24), a plurality of main pads(28), a plurality of test element groups(30), and a plurality of wires(34). The chip regions(22) are formed on a semiconductor substrate. The scribe region(24) is used for dividing the chip regions. The main pads(28) are formed within the chip regions. The test element groups(30) are formed within the scribe region. The wires(34) are used for connecting the test element groups to the main pads.
Abstract translation: 目的：提供一种包括测试元件组的半导体器件，以增加晶片上形成的芯片的数量，并通过减小主芯片之间划线区域的宽度来提高生产率。 构成：包括测试元件组的半导体器件包括多个芯片区域（22），划线区域（24），多个主焊盘（28），多个测试元件组（30）和多个 导线（34）。 芯片区域（22）形成在半导体衬底上。 划线区域（24）用于分割芯片区域。 主焊盘（28）形成在芯片区域内。 测试元件组（30）形成在划线区域内。 电线（34）用于将测试元件组连接到主焊盘。
-
公开(公告)号：KR1020020036584A
公开(公告)日：2002-05-16
申请号：KR1020000066832
申请日：2000-11-10
Applicant: 삼성전자주식회사
IPC: H01L29/78
Abstract: PURPOSE: A silicon-on-insulator(SOI) transistor is provided to guarantee a silicide margin in a source/drain region of the SOI transistor, by making the source/drain region of the SOI transistor have the same structure as the source/drain region of a partially depleted SOI(PDSOI) transistor. CONSTITUTION: An insulation layer(310) is formed on a wafer(300). A semiconductor substrate(320) is formed on the insulation layer, having a trench. A gate electrode(340) is formed on the center of the trench, higher than the sidewall of the trench. A spacer(360) is formed on both sidewalls of the gate electrode, filling the trench. The source/drain region is formed under the spacer and in the exposed semiconductor substrate.
Abstract translation: 目的：提供绝缘体上硅（SOI）晶体管，以通过使SOI晶体管的源极/漏极区域具有与源极/漏极相同的结构来保证SOI晶体管的源极/漏极区域中的硅化物边界 部分耗尽的SOI（PDSOI）晶体管的区域。 构成：在晶片（300）上形成绝缘层（310）。 半导体衬底（320）形成在具有沟槽的绝缘层上。 栅极电极（340）形成在沟槽的中心，高于沟槽的侧壁。 间隔物（360）形成在栅电极的两个侧壁上，填充沟槽。 源极/漏极区域形成在间隔物之下和暴露的半导体衬底中。
-
Patent Agency Ranking
公开(公告)号：KR100393221B1
公开(公告)日：2003-07-31
申请号：KR1020010019943
申请日：2001-04-13
Applicant: 삼성전자주식회사
IPC: H01L29/78
Abstract: PURPOSE: A silicon-on-insulator(SOI) field-effect-transistor(FET) including a body contact for removing a floating body effect is provided to reduce an occupying area and to prevent an abnormal operation of a circuit caused by contact capacitance, by eliminating the need to additionally form an metal interconnection for supplying power source to a body. CONSTITUTION: A buried oxide layer(51) is formed on a semiconductor substrate(50). The body constituting an active region is formed on the buried oxide layer. A gate oxide layer(48) is formed on the body. A gate(46) is formed on the gate oxide layer. The body contact(442) supplies the power source to the body. A trench penetrates an isolation region(41) surrounding the body, the body and the buried oxide layer. A conductive supplement is filled in the trench to electrically connect the body with the semiconductor substrate.
Abstract translation: 目的：提供包括用于除去浮体效应的体触点的绝缘体上硅（SOI）场效应晶体管（FET），以减小占用面积并防止由接触电容引起的电路的异常操作， 通过消除附加地形成用于将电源供应到身体的金属互连的需要。 构成：埋入氧化物层（51）形成在半导体衬底（50）上。 构成有源区的主体形成在掩埋氧化物层上。 栅氧化层（48）形成在主体上。 栅极（46）形成在栅极氧化物层上。 身体接触（442）将电源提供给身体。 沟槽穿透围绕主体，主体和掩埋氧化物层的隔离区域（41）。 导电补充物填充在沟槽中以将本体与半导体衬底电连接。
-
公开(公告)号：KR1020010026460A
公开(公告)日：2001-04-06
申请号：KR1019990037792
申请日：1999-09-07
Applicant: 삼성전자주식회사
IPC: H01L21/3205
Abstract: PURPOSE: A method for manufacturing a gate structure of a semiconductor device is provided to prevent impurities from penetrating a gate polysilicon layer, by additionally forming an impurity penetration blocking layer on a gate structure. CONSTITUTION: An insulating layer is formed on a semiconductor substrate(100). A gate polysilicon layer(120) is formed on the insulating layer. The first conductive layer(130) is formed on the polysilicon layer. An impurity penetration blocking layer(140) is formed on the first conductive layer. The stacked structure on the substrate is etched according to a selected gate pattern to form a gate structure.
Abstract translation: 目的：提供一种用于制造半导体器件的栅极结构的方法，以通过在栅极结构上另外形成杂质穿透阻挡层来防止杂质穿透栅极多晶硅层。 构成：在半导体衬底（100）上形成绝缘层。 在绝缘层上形成栅极多晶硅层（120）。 第一导电层（130）形成在多晶硅层上。 在第一导电层上形成杂质穿透阻挡层（140）。 根据选定的栅极图案蚀刻衬底上的层叠结构以形成栅极结构。
-
-
公开(公告)号：KR100389040B1
公开(公告)日：2003-06-25
申请号：KR1020000061257
申请日：2000-10-18
Applicant: 삼성전자주식회사
IPC: G11C29/00
CPC classification number: G11C17/16
Abstract: In a fuse circuit including programmable fuses in a semiconductor integrated circuit, the fuses store specific information related to the semiconductor integrated circuit, such as redundancy information, wafer lot number, die lot number, and die position on the wafer, etc. The fuse circuit utilizes a plurality of fuses for storing identical bit information. Consequently, in the case where a fuse has not been cut out correctly, the fuse circuit can reduce programming defects, whereby defect generation rates are remarkably decreased.
Abstract translation: 在包括半导体集成电路中的可编程熔丝的熔丝电路中，熔丝存储与半导体集成电路有关的特定信息，诸如冗余信息，晶片批号，管芯批号和晶片上的管芯位置等。熔丝电路 利用多个熔丝来存储相同的位信息。 因此，在保险丝未被正确切断的情况下，熔丝电路可以减少编程缺陷，由此缺陷产生率显着降低。
-
公开(公告)号：KR1020020013700A
公开(公告)日：2002-02-21
申请号：KR1020010019943
申请日：2001-04-13
Applicant: 삼성전자주식회사
IPC: H01L29/78
Abstract: PURPOSE: A silicon-on-insulator(SOI) field-effect-transistor(FET) including a body contact for removing a floating body effect is provided to reduce an occupying area and to prevent an abnormal operation of a circuit caused by contact capacitance, by eliminating the need to additionally form an metal interconnection for supplying power source to a body. CONSTITUTION: A buried oxide layer(51) is formed on a semiconductor substrate(50). The body constituting an active region is formed on the buried oxide layer. A gate oxide layer(48) is formed on the body. A gate(46) is formed on the gate oxide layer. The body contact(442) supplies the power source to the body. A trench penetrates an isolation region(41) surrounding the body, the body and the buried oxide layer. A conductive supplement is filled in the trench to electrically connect the body with the semiconductor substrate.
Abstract translation: 目的：提供包括用于去除浮体效应的体接触的绝缘体上硅（SOI）场效应晶体管（FET），以减少占用面积并防止由接触电容引起的电路的异常操作， 通过不需要另外形成用于向身体供电的金属互连。 构成：在半导体衬底（50）上形成掩埋氧化物层（51）。 在掩埋氧化物层上形成构成有源区的主体。 在主体上形成栅极氧化物层（48）。 栅极（46）形成在栅极氧化物层上。 身体接触（442）将电源供应到身体。 沟槽穿透围绕身体，身体和掩埋氧化物层的隔离区域（41）。 导电补充剂填充在沟槽中以将本体与半导体衬底电连接。
-
-
-
-
-
-
-
-
-
Search Results
12
records
(took 0.019 seconds)
