公开(公告)号：KR101616555B1

公开(公告)日：2016-04-29

申请号：KR1020090063630

申请日：2009-07-13

Applicant: 삼성전자주식회사

Inventor： 박선이 ,  박영훈 ,  한주철 ,  정진국 ,  강기호 ,  안유진

IPC: H01L21/28

CPC classification number: H01L21/76877 ,  H01L21/76834 ,  H01L21/76883 ,  H01L28/60

Abstract: 반도체장치의금속배선형성방법을제공한다. 구리막을형성하는공정과구리막을평탄화하는공정사이에서로다른온도에서두 번의열처리공정들이수행된다.

公开(公告)号：KR1020120110193A

公开(公告)日：2012-10-10

申请号：KR1020110027899

申请日：2011-03-29

Applicant: 삼성전자주식회사

Inventor： 최상준 ,  구준모 ,  이덕형 ,  신종철 ,  안유진 ,  박은경 ,  박선이

IPC: H01L27/146 ,  H01L21/324

CPC classification number: H01L27/14683 ,  H01L21/2652 ,  H01L21/268 ,  H01L27/14632 ,  H01L31/1872 ,  Y02E10/50 ,  Y02P70/521

Abstract: PURPOSE: An impurity doping method and a manufacturing method of a CMOS(Complementary Metal Oxide Semiconductor) image sensor using the same are provided to control the generation of a dark current or a luminous dot by eliminating an electron discharged from a dangling bond of a silicon substrate. CONSTITUTION: An amorphous layer is formed on a substrate(100) by a chemical vapor deposition method, an atomic layer deposition method, or a sputtering method. A first doping region is formed on the upper side of the substrate by injecting impurities through the upper side of the amorphous layer. The first doping region is transformed into a second doping region(130) through a laser annealing process. The amorphous layer is transformed into a re-crystallized layer(140). The re-crystallized layer is eliminated.

Abstract translation: 目的：提供使用其的CMOS（互补金属氧化物半导体）图像传感器的杂质掺杂方法和制造方法，以通过消除从硅悬挂键排出的电子来控制暗电流或发光点的产生 基质。 构成：通过化学气相沉积法，原子层沉积法或溅射法在基底（100）上形成非晶层。 通过从非晶层的上侧注入杂质，在衬底的上侧形成第一掺杂区域。 第一掺杂区域通过激光退火工艺转变成第二掺杂区域（130）。 将非晶层转变成再结晶层（140）。 消除再结晶层。

公开(公告)号：KR1020110006135A

公开(公告)日：2011-01-20

申请号：KR1020090063630

申请日：2009-07-13

Applicant: 삼성전자주식회사

Inventor： 박선이 ,  박영훈 ,  한주철 ,  정진국 ,  강기호 ,  안유진

IPC: H01L21/28

CPC classification number: H01L21/76877 ,  H01L21/76834 ,  H01L21/76883 ,  H01L28/60

Abstract: PURPOSE: A metal wiring forming method of a semiconductor device, capable of preventing the formation of a void is provided to prevent the hillock of a copper wiring due to the thermal and mechanical stresses by implementing heat process twice. CONSTITUTION: A copper layer is formed on a semiconductor substrate(S1). The copper layer is heat-treated in a first temperature(S2). The copper layer is heat-treated in a second temperature(S3). The copper wiring is formed by patterning the copper layer(S4). An anti oxidation layer is formed on the copper wiring in the third temperature(S5).

Abstract translation: 目的：提供能够防止形成空隙的半导体器件的金属布线形成方法，以通过两次实施热处理来防止由于热和机械应力引起的铜布线的小丘。 构成：在半导体衬底上形成铜层（S1）。 在第一温度（S2）中对铜层进行热处理。 在第二温度下对铜层进行热处理（S3）。 通过图案化铜层形成铜布线（S4）。 在第三温度下在铜布线上形成抗氧化层（S5）。