公开(公告)号：KR1020100070157A

公开(公告)日：2010-06-25

申请号：KR1020080128771

申请日：2008-12-17

Applicant: 삼성전자주식회사

Inventor： 송기환 ,  탁남균

IPC: G11C16/34 ,  G11C29/04 ,  G11C16/10 ,  G11C16/12

CPC classification number: H01L23/5252 ,  G11C17/18 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PURPOSE: A transistor dielectric rupture type anti-fuse utilizing chisel or CHISHL, and program circuit having it are provided to program data under low voltage by destructing a dielectric adjacent to a drain of a transistor. CONSTITUTION: A substrate(15) has a first conductivity type. A source(13) and drain(14) have a second conductive type and are separated from a predetermined domain within a substrate. A dielectric(12) is formed between source and drain on the top of substrate. The transistor comprises a gate(11) formed on the top of the dielectric. The dielectric between the gate and the substrate which is adjacent to the drain is destroyed.

Abstract translation: 目的：提供一种使用凿子或CHISHL的晶体管介质断裂型抗熔丝及其编程电路，通过破坏与晶体管的漏极相邻的电介质来在低电压下编程数据。 构成：衬底（15）具有第一导电类型。 源极（13）和漏极（14）具有第二导电类型并且与衬底内的预定域分离。 在衬底顶部的源极和漏极之间形成电介质（12）。 晶体管包括形成在电介质顶部上的栅极（11）。 与漏极相邻的栅极和衬底之间的电介质被破坏。

公开(公告)号：KR100801707B1

公开(公告)日：2008-02-11

申请号：KR1020060126831

申请日：2006-12-13

Applicant: 삼성전자주식회사

Inventor： 탁남균 ,  송기환

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10802 ,  H01L21/84 ,  H01L27/108 ,  H01L27/10844 ,  H01L27/1203 ,  H01L29/7841

Abstract: A floating-body memory and a method for fabricating the same are provided to reduce junction capacitance by arranging leakage shielding patterns between a floating body and first source/drain regions. A semiconductor substrate(11) includes a cell region and a peripheral region. A floating body memory cell is arranged on the cell region of the semiconductor substrate. A first floating body(22) is arranged on the peripheral region of the semiconductor substrate. A peripheral gate pattern(48) is arranged on the first floating body. A plurality of first source/drain regions(58,60) are arranged at both sides of the peripheral gate pattern. A plurality of first leakage shielding patterns(52P) are arranged between the first floating body and the first source/drain regions. The first source/drain regions contact with the first floating body.

Abstract translation: 提供浮体存储器及其制造方法，以通过在浮体和第一源极/漏极区域之间布置泄漏屏蔽图案来减小结电容。 半导体衬底（11）包括单元区域和周边区域。 在半导体衬底的单元区域上布置浮体存储单元。 第一浮体（22）布置在半导体衬底的周边区域上。 外围门图案（48）布置在第一浮体上。 多个第一源极/漏极区域（58,60）布置在外围栅极图案的两侧。 多个第一泄漏屏蔽图案（52P）布置在第一浮体和第一源极/漏极区之间。 第一源极/漏极区域与第一浮体接触。

公开(公告)号：KR101461629B1

公开(公告)日：2014-11-20

申请号：KR1020080069564

申请日：2008-07-17

Applicant: 삼성전자주식회사

Inventor： 송기환 ,  탁남균

IPC: G11C7/00 ,  G11C11/40 ,  G11C5/14

Abstract: 본 발명은 바이폴라 접합 트랜지스터(바이폴라 접합 트랜지스터(BJT)) 동작을 사용하는 메모리 셀 구조들, 메모리 어레이들, 메모리 장치들, 메모리 제어기들, 및 메모리 시스템들이 공개한다. 이 장치는 복수개의 메모리 셀들을 구비하는 메모리 어레이 및 제어부를 구비하고, 복수개의 메모리 셀들 각각은 적어도 하나의 비트 라인, 적어도 하나의 소스 라인 및 적어도 하나의 워드 라인 각각에 연결된 제1 노드, 제2노드 및 게이트 노드를 구비하는 플로팅 바디 트랜지스터를 구비하고, 제어부는 적어도 하나의 소스 라인 및 적어도 하나의 비트 라인의 하나를 선택함에 의해서 리프레쉬 명령에 응답하여 리프레쉬 동작을 수행하도록 하고, 만일 제1 데이터가 선택된 라인에 연결된 메모리 셀에 저장되면, 바이폴라 접합 트랜지스터 동작에 의해서 유발되는 제1전류가 흐르게 된다.

公开(公告)号：KR1020090009699A

公开(公告)日：2009-01-23

申请号：KR1020080055182

申请日：2008-06-12

Applicant: 삼성전자주식회사

Inventor： 송기환 ,  탁남균

IPC: G11C7/00 ,  G11C5/14

CPC classification number: G11C11/4096 ,  G11C11/406 ,  G11C11/4085 ,  G11C11/4094

Abstract: A semiconductor memory device including capacitor-less dynamic memory cell, a dynamic memory cell for the same, and a memory system including the same are provided to reduce refresh operation time by supplying refresh control signals to all bit lines and all source lines at the same time. A memory cell array(50) writes/reads data 1 or data 0. A row control part(52) selects memory cells by controlling word lines(WL1-WLi) and source lines(SL1-SLi) in response to write signals(WR)/read signals(RD) and address signals(ADD), and refreshes the memory cells by controlling the source lines in response to refresh orders(REF). A column control part(54) prevents write/read operation of data in non-selected memory cells by controlling the bit lines in response to the write signals/the read signals and the address signals, writes/reads data 1 or data 0 from the selected memory cell, and refreshes the memory cells by controlling the bit lines(BL1-BLj) in response to the refresh orders.

Abstract translation: 提供了包括无电容动态存储单元的半导体存储器件，用于其的动态存储单元和包括该存储单元的存储器单元以及包括该半导体存储单元的存储器单元，以通过向所有位线和所有源极线提供刷新控制信号来减少刷新操作时间 时间。 存储单元阵列（50）写入/读取数据1或数据0.行控制部分（52）通过响应于写入信号（WR）控制字线（WL1-WLi）和源极线（SL1-SLi）来选择存储单元 ）/读信号（RD）和地址信号（ADD），并且通过响应于刷新顺序（REF）控制源线来刷新存储器单元。 列控制部分（54）通过响应于写信号/读信号和地址信号控制位线，从数据1或数据0写入/读取数据1或数据0来防止数据在未选择的存储单元中的写/ 并且通过响应于刷新顺序控制位线（BL1-BLj）来刷新存储器单元。

公开(公告)号：KR100773355B1

公开(公告)日：2007-11-05

申请号：KR1020060107345

申请日：2006-11-01

Applicant: 삼성전자주식회사

Inventor： 탁남균 ,  송기환

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L27/10841 ,  H01L27/10864 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/66666 ,  H01L29/7827

Abstract: A single transistor memory cell having insulation regions between a source/drain region and a bulk region and a manufacturing method thereof are provided to improve the data retention property of the memory cell by decreasing a junction area in the source/drain region. A single transistor memory cell includes an active semiconductor pattern(55a), a recessed region(R), first and second insulation regions(77s,77d), and a gate electrode(69g). The active semiconductor pattern includes a bulk region and a dopant region, which are sequentially laminated on a semiconductor substrate. The active semiconductor pattern is insulated from the semiconductor substrate. The recessed region penetrates the dopant region to separate the dopant region into a source region and a drain region. First and second sidewalls of the recessed region are adjacent to the source and drain regions, respectively. The first insulation region is applied between the source region and the bulk region to be apart from the first sidewall. The second insulation region is applied between the drain region and the bulk region to be apart from the second sidewall. The recessed region is filled with the gate electrode.

Abstract translation: 提供具有源极/漏极区域和体区域之间的绝缘区域的单晶体管存储单元及其制造方法，以通过减小源/漏区域中的结面积来改善存储单元的数据保持性能。 单晶体管存储单元包括有源半导体图案（55a），凹陷区域（R），第一和第二绝缘区域（77s，77d）和栅极电极（69g）。 有源半导体图案包括依次层叠在半导体衬底上的体区域和掺杂剂区域。 有源半导体图案与半导体衬底绝缘。 凹陷区域穿透掺杂剂区域以将掺杂剂区域分离成源极区域和漏极区域。 凹陷区域的第一和第二侧壁分别与源极和漏极区域相邻。 第一绝缘区域被施加在源极区域和主体区域之间以与第一侧壁分开。 第二绝缘区域被施加在漏极区域和主体区域之间以与第二侧壁分开。 凹陷区域被栅电极填充。

公开(公告)号：KR1020100040031A

公开(公告)日：2010-04-19

申请号：KR1020080099064

申请日：2008-10-09

Applicant: 삼성전자주식회사

Inventor： 탁남균 ,  송기환

IPC: H01L29/78

CPC classification number: H01L29/7841 ,  H01L21/28114 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/1203 ,  H01L29/41733 ,  H01L29/66553 ,  H01L29/7843 ,  H01L29/7846

Abstract: PURPOSE: A transistor, a method for forming the same and a semiconductor memory cell including the same are provided to reduce a gate induced drain leakage current by forming information storage element under space patterns which are located on a gate pattern and on the sidewall of the pattern. CONSTITUTION: A first semiconductor region(80) is formed on a semiconductor substrate(10). Gate patterns(90) are arranged on the first semiconductor region. Spacer patterns(78, 105) are arranged on the sidewall of the gate patterns. The first semiconductor region, a second semiconductor region and a third semiconductor region are successively arranged under the gate pattern and the spacer patterns and around the spacer patterns.

Abstract translation: 目的：提供晶体管，其形成方法和包括该晶体管的半导体存储单元，以通过在位于栅极图案和栅极图案的侧壁上的空间图案之下形成信息存储元件来减小栅极感应漏极泄漏电流 模式。 构成：在半导体衬底（10）上形成第一半导体区域（80）。 栅极图案（90）布置在第一半导体区域上。 间隔图案（78,105）布置在栅极图案的侧壁上。 第一半导体区域，第二半导体区域和第三半导体区域依次布置在栅极图案和间隔物图案之下并且围绕间隔物图案。

公开(公告)号：KR1020090022748A

公开(公告)日：2009-03-04

申请号：KR1020070088362

申请日：2007-08-31

Applicant: 삼성전자주식회사

Inventor： 탁남균 ,  송기환 ,  윤은정

IPC: H01L21/8242 ,  H01L27/108

Abstract: A method of fabricating one-transistor floating body dram is provided to improve electrical property by minimizing electrical interaction between the increased source area the drain region. A method of fabricating one-transistor floating body dram is comprised of the step: forming a semiconductor film, forming an isolation film, and forming a buried gap. A semiconductor substrate has a cell region and a peripheral area. A sacrificing layer is formed on the cell region and is not formed on the peripheral area of the substrate. A semiconductor film is formed on the sacrificing layer of the cell region and semiconductor substrate of the peripheral area. The isolation film is formed on the semiconductor film and sacrificing layer and restricts a floating body.

Abstract translation: 提供一种制造单晶体体浮体电极的方法，通过最小化漏极区域的增加的源区域之间的电相互作用来改善电性能。 制造单晶体管浮体体的方法包括以下步骤：形成半导体膜，形成隔离膜，形成埋入间隙。 半导体衬底具有单元区域和周边区域。 在单元区域上形成牺牲层，并且不形成在基板的周边区域上。 半导体膜形成在周边区域的单元区域和半导体基板的牺牲层上。 隔离膜形成在半导体膜和牺牲层上并限制浮体。

公开(公告)号：KR100819553B1

公开(公告)日：2008-04-07

申请号：KR1020060119087

申请日：2006-11-29

Applicant: 삼성전자주식회사

Inventor： 탁남균 ,  송기환 ,  오창우 ,  조우영

IPC: H01L27/108 ,  H01L21/8242

CPC classification number: H01L29/7841 ,  H01L27/10802

Abstract: A one-transistor floating-body DRAM device and a method for manufacturing the same are provided to achieve excellent data retention by minimizing a contact surface between source/drain regions and a floating body through leakage shield patterns. A floating body(55) is arranged on a semiconductor substrate(51). A gate electrode(63) is arranged on the floating body. Source/drain regions(73) are arranged at both sides of the floating body. Leakage shield patterns(71') are arranged between the floating body and the source/drain regions. The floating body has an excess carrier storage region(55S). The source/drain regions are contacted to the floating body. The leakage shield patterns are aligned at an external side of the gate electrode. The leakage shield patterns are contacted to bottoms of the source/drain regions. The floating body is arranged between the source/drain regions and extended to lower portions of the leakage shield patterns.

Abstract translation: 提供单晶体管浮体DRAM器件及其制造方法，以通过使泄漏屏蔽图案最小化源极/漏极区域与浮体之间的接触表面来实现优异的数据保持。 浮体（55）布置在半导体衬底（51）上。 在浮体上设置栅电极（63）。 源极/漏极区域（73）布置在浮体的两侧。 泄漏屏蔽图案（71'）布置在浮体和源/漏区之间。 浮体具有过量的载体储存区域（55S）。 源极/漏极区域与浮体接触。 泄漏屏蔽图案在栅电极的外侧对准。 泄漏屏蔽图案与源极/漏极区域的底部接触。 浮体布置在源极/漏极区域之间并延伸到泄漏屏蔽图案的下部。

公开(公告)号：KR100734298B1

公开(公告)日：2007-07-02

申请号：KR1020050135871

申请日：2005-12-30

Applicant: 삼성전자주식회사

Inventor： 탁남균 ,  김창현 ,  이영택 ,  현재웅

IPC: G11B7/00 ,  G11B20/04

Abstract: A pattern recognition-type optical memory using light and a data processing device for recording/reading data are provided to read data from the memory by using light or to store data in the memory, and to form plural pattern types, thereby realizing multiple bits, consequently high integration is enabled while high-speed data processing is available. A light source(120) generates light to sense patterns formed in a pattern recognition-type optical memory(110) by using the light. An image detector(140) receives the light selectively passing through a substrate and a pattern layer formed on the substrate, detects an image corresponding to patterns formed on the substrate, and provides an image signal having different amounts of light by corresponding to pattern types of the image. A photoelectric converter(150) inputs the image signal to convert the image signal into an electric signal.

Abstract translation: 提供使用光的图案识别型光存储器和用于记录/读取数据的数据处理装置，以通过使用光从存储器读取数据或将数据存储在存储器中并形成多个图案类型，从而实现多个位， 因此在高速数据处理可用的情况下实现高集成度。 光源（120）通过使用该光产生光以感测形成在模式识别型光存储器（110）中的图案。 图像检测器（140）接收选择性地穿过衬底和形成在衬底上的图案层的光，检测与形成在衬底上的图案相对应的图像，并且通过对应于图案类型的图案提供具有不同光量的图像信号 图片。 光电转换器（150）输入图像信号以将图像信号转换为电信号。

公开(公告)号：KR100672032B1

公开(公告)日：2007-01-19

申请号：KR1020050127690

申请日：2005-12-22

Applicant: 삼성전자주식회사

Inventor： 탁남균 ,  송기환

IPC: H01L29/78 ,  H01L29/86

CPC classification number: H03F3/45183 ,  H01L27/0207 ,  H01L27/10897 ,  H01L29/66666 ,  H03F3/195 ,  H03F3/45188 ,  H03F2203/45292 ,  H03F2203/45352 ,  H01L29/7827

Abstract: A semiconductor circuit is provided to improve the degree of integration and to improve characteristics of the semiconductor circuit itself by using an improved vertical transistor structure. A semiconductor circuit includes an amplifying transistor pair, a load portion, and a current source. The amplifying transistor pair includes two transistors. The amplifying transistor pair is used for amplifying a differential input signal and outputting the amplified differential input signal. The load portion is located at a portion between a first power source and the amplifying transistor pair. The current source is located between the amplifying transistor pair and a second power source. The current source is used as a current path between the first and the second power sources. Each transistor of the amplifying transistor pair includes a drain(341) of an upper portion and a source(343) of a lower portion.

Abstract translation: 提供半导体电路以通过使用改进的垂直晶体管结构来提高集成度并改善半导体电路本身的特性。 半导体电路包括放大晶体管对，负载部分和电流源。 放大晶体管对包括两个晶体管。 放大晶体管对用于放大差分输入信号并输出​​放大的差分输入信号。 负载部分位于第一电源和放大晶体管对之间的部分。 电流源位于放大晶体管对和第二电源之间。 电流源用作第一和第二电源之间的电流路径。 放大晶体管对的每个晶体管包括上部的漏极（341）和下部的源极（343）。