公开(公告)号：KR1020080071809A

公开(公告)日：2008-08-05

申请号：KR1020070010126

申请日：2007-01-31

Applicant: 삼성전자주식회사

Inventor： 박철우 ,  윤병문 ,  이원준 ,  송은봉

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/66621 ,  H01L21/3063 ,  H01L21/3086 ,  H01L29/1037 ,  H01L29/4236

Abstract: A method of forming a semiconductor device is provided to increase the width of an aperture defined by a mask pattern to be equal to or greater than an upper width of a trench by isotropy-etching a mask pattern used for forming the trench. A mask pattern(112) having a first aperture is formed on a substrate. An active region and a field region are defined on the substrate. The first aperture opens a portion of the substrate. The substrate is etched by using the mask pattern as an etch mask, such that a first trench is formed on the active and field regions. A second aperture(118) is formed by isotropy-etching the mask pattern. The second aperture is greater than the first aperture. A second trench is formed by rinsing the substrate, such that a natural oxide film is removed from the substrate. An inner width of the first trench(116), which is formed in the field region, is selectively extended to form the second trench. A gate is formed in the second trench.

Abstract translation: 提供一种形成半导体器件的方法，通过各向同性蚀刻用于形成沟槽的掩模图案，将由掩模图案限定的孔的宽度增加到等于或大于沟槽的上部宽度。 具有第一孔的掩模图案（112）形成在基板上。 在衬底上限定有源区和场区。 第一孔打开衬底的一部分。 通过使用掩模图案作为蚀刻掩模蚀刻衬底，使得在有源场和场区上形成第一沟槽。 通过各向同性蚀刻掩模图案形成第二孔（118）。 第二孔径大于第一孔径。 通过冲洗衬底形成第二沟槽，从而从衬底去除自然氧化膜。 在场区域中形成的第一沟槽（116）的内部宽度被选择性地延伸以形成第二沟槽。 在第二沟槽中形成栅极。

公开(公告)号：KR1020080106695A

公开(公告)日：2008-12-09

申请号：KR1020070054440

申请日：2007-06-04

Applicant: 삼성전자주식회사

Inventor： 강현아 ,  송은봉 ,  이원준

IPC: C09K13/08 ,  C09K13/06 ,  C09K13/04

CPC classification number: C09K13/08 ,  H01L21/30604

Abstract: A chemical etchant is provided to selectively and uniformly etch one among impurity regions injected with the different impurity ions. A chemical etchant comprises a mixed solution consisting of a hydrofluoric acid(HF), nitric acid(HNO3), phosphoric acid(H3PO4), acetic acid(CH3COOH) and water. The volume composition ratio of hydrofluoric acid(HF), nitric acid(HNO3), phosphoric acid(H3PO4), acetic acid(CH3COOH) and water is respective 0.8 - 1.2 Vol%, 2.8 - 3.2 Vol%, 0.25 - 3.0 Vol%, 4.0 - 7.75 Vol% and 84.85 - 92.15 Vol%.

Abstract translation: 提供化学蚀刻剂以选择性地和均匀地蚀刻注入了不同杂质离子的杂质区域之一。 化学蚀刻剂包括由氢氟酸（HF），硝酸（HNO 3），磷酸（H 3 PO 4），乙酸（CH 3 COOH）和水组成的混合溶液。 氢氟酸（HF），硝酸（HNO 3），磷酸（H 3 PO 4），乙酸（CH 3 COOH）和水的体积组成比分别为0.8〜1.2vol％，2.8〜3.2vol％，0.25〜3.0vol％ 4.0-7.75vol％和84.85-92.15vol％。

公开(公告)号：KR1020070082921A

公开(公告)日：2007-08-23

申请号：KR1020060015969

申请日：2006-02-20

Applicant: 삼성전자주식회사

Inventor： 송은봉 ,  전정식 ,  안태혁 ,  김동현

IPC: H01L21/76 ,  H01L21/336

CPC classification number: H01L21/76229 ,  H01L29/66795

Abstract: A method for fabricating an isolation layer of a fin-type FET is provided to remarkably decrease the number of process for fabricating a fin-type FET by forming isolation layers having different steps in the peripheral and cell regions of a substrate by a minimized process. A substrate(100) divided into a cell region and a peripheral region that are exposed to an opening of a hard mask pattern is etched to form a trench so that a silicon fin(110) is defined by the trench to be guaranteed as the channel region of the fin-type transistor. A liner layer(112) having substantially the same thickness is formed on the bottom and the top surfaces of the trench and on the surface of the hard mask pattern. A planarized insulation layer is formed to fill the trench having the liner layer. A photoresist pattern is formed to cover the insulation layer in the peripheral region. A part of the insulation layer in the cell region is firstly wet-etched to form an insulation layer pattern. The photoresist pattern is removed. While the liner layer and the hard mask pattern are removed by a second wet-etch process, the insulation layer in the cell region and a part of the upper part of the insulation layer pattern in the cell region are etched to form isolation layers(120a,120b) having different heights in the peripheral and cell regions.

Abstract translation: 提供一种用于制造鳍型FET的隔离层的方法，通过以最小化的工艺在基板的外围和单元区域中形成具有不同步骤的隔离层，从而显着地减少了制造鳍式FET的工艺数量。 蚀刻分割成暴露于硬掩模图案的开口的单元区域和周边区域的基板（100），以形成沟槽，从而由沟槽限定硅片（110）以保证作为沟道 鳍式晶体管的区域。 在沟槽的底部和顶表面以及硬掩模图案的表面上形成具有基本相同厚度的衬垫层（112）。 形成平坦化的绝缘层以填充具有衬里层的沟槽。 形成光致抗蚀剂图案以覆盖周边区域中的绝缘层。 首先对细胞区域中的绝缘层的一部分进行湿法蚀刻以形成绝缘层图案。 去除光致抗蚀剂图案。 虽然通过第二湿蚀刻工艺去除衬里层和硬掩模图案，但是蚀刻单元区域中的绝缘层和单元区域中的绝缘层图案的上部的一部分以形成隔离层（120a ，120b）在外周和细胞区域具有不同的高度。