公开(公告)号：KR1020050020375A

公开(公告)日：2005-03-04

申请号：KR1020030058275

申请日：2003-08-22

Applicant: 삼성전자주식회사

Inventor： 임원철 ,  양선모

IPC: H01L21/60

CPC classification number: H01L2224/10 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/78301 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: PURPOSE: A method of attaching a solder ball to a semiconductor package and the semiconductor package manufactured thereby are provided to improve the intensity of attachment of a solder ball by embedding a ball bump or a wire loop connected with a solder ball land into the solder ball. CONSTITUTION: Solder ball lands(12) of a substrate(11) are exposed to the outside by using a solder mask(13) with a predetermined pattern. A gold ball(22a) is attached on each solder ball land by using wire-bonding. By cutting a gold wire(21a) connected with the gold ball, a plurality of ball bumps are formed on the solder ball land. A flux is coated on the solder ball land. A ball bump embedded in solder ball(15) is formed on the solder ball land by using a re-flow manner.

Abstract translation: 目的：将焊球附着到半导体封装件和由此制造的半导体封装件的方法被提供，以通过将与球焊盘连接的焊球或引线环嵌入焊球来提高焊球的附着强度 。 构成：通过使用具有预定图案的焊接掩模（13）将基板（11）的焊球台（12）暴露于外部。 通过使用引线接合将金球（22a）附接在每个焊球上。 通过切割与金球连接的金线（21a），在焊球上形成多个球凸块。 焊剂涂在焊球上。 通过使用回流方式在焊球上形成嵌入焊球（15）中的球凸点。

公开(公告)号：KR1020000018709A

公开(公告)日：2000-04-06

申请号：KR1019980036436

申请日：1998-09-04

Applicant: 삼성전자주식회사

Inventor： 장석홍 ,  양선모

IPC: H01L21/50

Abstract: PURPOSE: A wire bonding device for a ball grid array(BGA) directly checks a good bonding or fail bonding in a wire bonding time point at which a bonding pad formed in a chip of BGA package and a pattern of PCB are bonded. CONSTITUTION: A wire bonding device for BGA includes a capillary mounted to XY table in order to perform a wire bonding about PCB pattern and a bonding pad, a heater block body(65), a heater block adapter(69), a bonding temperature regulator, and a pattern recognition device and a control unit(10). The heater block body is fixed to a working table in order to heat the PCB with a proper temperature for the wire bonding. The heater block adapter is connected to a heater block body(65), and fixes the PCB by a suction. The bonding temperature regulator includes the heater block body and the heater block adapter. A pattern recognition device and control unit recognize a PCB pattern and a chip pattern. Each solder ball pad is grounded by a grounding part mounted to the heater block adapter. The solder ball pad is formed on a back side of the PCB in order to achieve an electrical connection of the PCB formed on its front side. Thereby, the wire bonding device immediately checks a good bonding or fail bonding in a wire bonding.

Abstract translation: 目的：用于球栅阵列（BGA）的引线接合装置在形成于BGA封装的芯片中的焊盘与PCB的图案相结合的引线接合时间点中直接检查良好的接合或失效接合。 构成：用于BGA的引线接合装置包括安装到XY工作台的毛细管，以便执行关于PCB图案的引线键合和焊盘，加热器块体（65），加热器块适配器（69），接合温度调节器 ，以及图案识别装置和控制单元（10）。 将加热块体固定在工作台上，以便以适当的温度加热PCB，以实现引线接合。 加热器块适配器连接到加热块体（65），并通过吸力固定PCB。 接合温度调节器包括加热块体和加热器块适配器。 图案识别装置和控制单元识别PCB图案和芯片图案。 每个焊球垫由安装在加热块适配器上的接地部分接地。 焊锡球焊盘形成在PCB的背面，以便实现在其正面上形成的PCB的电连接。 由此，引线接合装置立即检查引线接合中的良好的接合或失败接合。

公开(公告)号：KR1020060059574A

公开(公告)日：2006-06-02

申请号：KR1020040098701

申请日：2004-11-29

Applicant: 삼성전자주식회사

Inventor： 양선모 ,  이근아

IPC: H01L23/28

CPC classification number: H01L23/481 ,  H01L23/28 ,  H01L23/5389

Abstract: 본 발명은 기판에 관통홀이 형성된 반도체 패키지에 관한 것으로, 칩 실장 영역에 다수의 관통홀이 형성된 기판; 상기 기판의 칩 실장 영역에 필름형 접착제에 의하여 부착되는 반도체 칩; 상기 반도체 칩과 기판을 전기적으로 연결하는 연결수단; 및 상기 기판의 상면과 반도체 칩, 연결수단을 봉지한 수지 봉지부;를 포함하며, 상기 수지 봉지부를 형성할 때 상기 기판과 접착제 사이에 잔존하는 공기가 관통홀을 통하여 빠져나가는 것을 특징으로 한다. 본 발명에 따른 기판에 관통홀이 형성된 반도체 패키지에 의하면 기판과 필름형 접착제 사이의 공기 트랩에 의한 보이드의 발생을 감소시켜 반도체 패키지의 신뢰성을 높일 수 있다.
반도체 패키지, 관통홀, 공기 트랩, 필름형 접착제, 패키지 크랙

公开(公告)号：KR1020050091932A

公开(公告)日：2005-09-16

申请号：KR1020040016414

申请日：2004-03-11

Applicant: 삼성전자주식회사

Inventor： 강인구 ,  안상호 ,  양선모

IPC: H01L21/60

CPC classification number: H01L24/85 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L25/0657 ,  H01L2224/03 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05599 ,  H01L2224/1134 ,  H01L2224/32145 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48451 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/48599 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/78301 ,  H01L2224/85051 ,  H01L2224/8518 ,  H01L2224/85186 ,  H01L2224/85986 ,  H01L2225/0651 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20651 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/4554 ,  H01L2224/85399

Abstract: A method and apparatus for bonding a wire and a wire bond device formed by the same are disclosed. The method includes providing a carrier with at least a first pad, providing a semiconductor chip having at least the second pad, the at least second pad being smaller than the first a pad, forming a conductive stud bump on the second pad, and forming a bonding wire that has two terminal portions, which are respectively bonded to the first pad and the stud bump to electrically connect the first pad and the second pad. The stud bump is bonded to the second pad by a ball bonding method which uses a wire that has an approximately smaller diameter than the bonding wire. Further, a prominence formed on one end of the terminal portions is provided which has an approximately larger diameter than the stud bump.

公开(公告)号：KR1020030012290A

公开(公告)日：2003-02-12

申请号：KR1020010046264

申请日：2001-07-31

Applicant: 삼성전자주식회사

Inventor： 양선모 ,  김동국

IPC: H01L21/78

CPC classification number: B23D59/001 ,  B28D5/0058 ,  B28D5/0094

Abstract: PURPOSE: An apparatus for cutting a wafer is provided to prevent a cutting error of a wafer by cutting back faces of semiconductor chips after recognizing shapes of the semiconductor chips. CONSTITUTION: A chuck table(10) is used for absorbing and aligning wafers according to control signals of a control portion(40). A predetermined hole(16) is formed on a center portion of the chuck table(10). A camera(20) is installed within the hole(16) in order to recognize shapes of semiconductor chips formed on a front face of a wafer and transmit recognized data to the control portion. A cutting blade(30) is used for cutting a back face of the wafer to divide the wafer into individual semiconductor chips. The control portion(40) is electrically connected with the chuck table(10), the camera(20), and the cutting blade(30) in order to control operations of the chuck table(10), the camera(20), and the cutting blade(30).

Abstract translation: 目的：提供一种用于切割晶片的设备，以在识别半导体芯片的形状之后，通过切割半导体芯片的背面来防止晶片的切割误差。 构成：卡盘台（10）用于根据控制部分（40）的控制信号吸收和对准晶片。 在卡盘台（10）的中心部分形成预定孔（16）。 摄像机（20）安装在孔（16）内，以便识别形成在晶片前表面上的半导体芯片的形状，并将识别的数据传送到控制部分。 切割刀片（30）用于切割晶片的背面以将晶片分成单独的半导体芯片。 控制部分（40）与卡盘台（10），相机（20）和切割刀片（30）电连接，以便控制卡盘台（10），照相机（20）和 切割刀片（30）。

公开(公告)号：KR100825797B1

公开(公告)日：2008-04-28

申请号：KR1020060130837

申请日：2006-12-20

Applicant: 삼성전자주식회사

Inventor： 김경만 ,  양선모 ,  한창훈

IPC: H01L23/28 ,  H01L21/301

CPC classification number: H01L24/85 ,  H01L23/49811 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/78 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/4807 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48229 ,  H01L2224/48451 ,  H01L2224/48453 ,  H01L2224/48464 ,  H01L2224/48479 ,  H01L2224/48599 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48699 ,  H01L2224/48724 ,  H01L2224/48744 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48824 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/73265 ,  H01L2224/78302 ,  H01L2224/85051 ,  H01L2224/85385 ,  H01L2224/85424 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2224/85455 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2224/48471 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/4554

Abstract: A semiconductor package and a method for manufacturing the same are provided to perform a wire bonding process on a fine finger by bonding a wire at an upper surface and a lateral surface of the finger. A substrate has a finger(111). One or more semiconductor chip having a chip pad is laminated on the substrate. A wire(160) is formed to connect electrically the finger and the chip pad to each other. One end of the wire is bonded with the finger at an upper surface of the finger and a lateral surface of the finger. A protrusion(162) is formed at one end of the wire. In a vertical projection of the substrate, a maximum width of an upper surface of the finger is smaller than a width of the protrusion. In the vertical projection of the substrate, the upper surface of the finger is positioned within a lower surface of the finger.

Abstract translation: 提供半导体封装及其制造方法，通过在手指的上表面和侧表面处接合线来对细指进行引线接合处理。 衬底具有手指（111）。 具有芯片焊盘的一个或多个半导体芯片层叠在基板上。 形成电线（160）以将手指和芯片焊盘彼此电连接。 线的一端在手指的上表面和手指的侧表面上与手指接合。 在导线的一端形成突起（162）。 在基板的垂直投影中，手指的上表面的最大宽度小于突起的宽度。 在基板的垂直投影中，手指的上表面位于手指的下表面内。

公开(公告)号：KR100604840B1

公开(公告)日：2006-07-28

申请号：KR1020040016414

申请日：2004-03-11

Applicant: 삼성전자주식회사

Inventor： 강인구 ,  안상호 ,  양선모

IPC: H01L21/60

CPC classification number: H01L24/85 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L25/0657 ,  H01L2224/03 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05599 ,  H01L2224/1134 ,  H01L2224/32145 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48451 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/48599 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/78301 ,  H01L2224/85051 ,  H01L2224/8518 ,  H01L2224/85186 ,  H01L2224/85986 ,  H01L2225/0651 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20651 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/4554 ,  H01L2224/85399

Abstract: 미세 피치 범프(fine pitch bump)에의 리버스 와이어 본딩(reverse wire bonding) 방법 및 이에 의한 와이어 본드 구조체를 제공한다. 본 발명의 일 관점에 따른 와이어 본딩 방법은, 적어도 제1패드를 가지는 캐리어(carrier) 및 제1패드에 비해 작은 크기의 제2패드를 가지는 반도체 칩을 제공한다. 제2패드 상에 도전성의 스터드 범프(stud bump)를 형성한다. 제1패드 상에 볼 본딩 형태(ball bonding fashion)의 본딩에 의해 스터드 범프에 비해 큰 직경을 가지게 형성된 돌기를 통해 제1패드에 전기적으로 연결되고 돌기에서 스터드 범프 상으로 연장되고 스터드 범프에 스티치 본딩 형태(stitch bonding fashion)로 본딩되어 제2패드에 전기적으로 연결되는 도전성의 본딩 와이어를 형성한다. 이때, 스터드 범프(stud bump)는 본딩 와이어에 비해 상대적으로 작은 직경을 가지는 와이어를 사용하여 볼 본딩 형태(ball bonding fashion)의 본딩에 의해 형성되는 돌기로서 제2패드 상에 부착되게 형성될 수 있다.
미세 패드, 리버스 본딩, 스터드 범프, 스위핑, 와이어 휨

公开(公告)号：KR1020030075860A

公开(公告)日：2003-09-26

申请号：KR1020020015329

申请日：2002-03-21

Applicant: 삼성전자주식회사

Inventor： 강인구 ,  안상호 ,  양선모

IPC: H01L23/12

CPC classification number: H01L24/85 ,  H01L24/29 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/05599 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/30505 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/73265 ,  H01L2224/83139 ,  H01L2224/85051 ,  H01L2224/85186 ,  H01L2224/85399 ,  H01L2224/85986 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01047 ,  H01L2924/07802 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/0715 ,  H01L2924/0665 ,  H01L2224/78 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/4554

Abstract: PURPOSE: A semiconductor chip stacked structure and a method for stacking a semiconductor chip are provided to be capable of minimizing the height of the semiconductor chip stacked structure regardless of the size of the first and second chip. CONSTITUTION: A semiconductor chip stacked structure(30) is provided with a substrate(31) including a chip adhering region(32a) and a line pattern(33), the first chip(34) having a plurality of first electrode pads(35), attached to the chip adhering region, the first metal bump(37) formed at each first electrode pad, the first bonding wire(38) for electrically connecting the first metal bump of the first chip to the substrate, an insulating liquid adhesive(39) coated at the active surface of the first chip, the second chip(40) stacked on the first chip using the insulating liquid adhesive, and the second bonding wire(44) for electrically connecting the second electrode pad of the second chip to the line pattern of the substrate.

Abstract translation: 目的：提供半导体芯片堆叠结构和堆叠半导体芯片的方法，以便能够使半导体芯片堆叠结构的高度最小化，而与第一和第二芯片的尺寸无关。 构成：半导体芯片堆叠结构（30）具有包括芯片接合区域（32a）和线路图案（33）的基板（31），第一芯片（34）具有多个第一电极焊盘（35） 在第一电极焊盘上形成的第一金属凸块（37），将第一芯片的第一金属凸块与基板电连接的第一接合线（38），绝缘液体粘合剂（39） ），使用绝缘液体粘合剂堆叠在第一芯片上的第二芯片（40）和用于将第二芯片的第二电极焊盘电连接到线路的第二接合线（44） 衬底图案。

公开(公告)号：KR100391264B1

公开(公告)日：2003-07-12

申请号：KR1020010046264

申请日：2001-07-31

Applicant: 삼성전자주식회사

Inventor： 양선모 ,  김동국

IPC: H01L21/78

CPC classification number: B23D59/001 ,  B28D5/0058 ,  B28D5/0094

Abstract: The present invention relates to an apparatus for cutting a wafer, wherein the wafer cutting process is performed along a back side of a wafer, a semiconductor chip being formed on the front side thereof, by cutting the wafer along the back side of the wafer by directly recognizing the semiconductor chip shape formed on the front side of the wafer thereby minimizing cutting defects due to sawing blade misalignment.The present invention includes a hole formed in the center portion of a chuck table on which the wafer, which is facing down, is attached and a camera installed under the hole of the chuck table. After the wafer is properly aligned by the camera recognizing the semiconductor chip shape formed on the front side of the wafer, a wafer cutting process is performed by a sawing blade.

Abstract translation: 切割晶片的装置技术领域本发明涉及一种用于切割晶片的装置，其中通过沿着晶片的背面切割晶片，沿晶片的背面执行晶片切割过程，半导体芯片形成在晶片的正面上， 直接识别形成在晶片正面上的半导体芯片形状，从而最小化由于锯片刀片未对准引起的切割缺陷。本发明包括形成在卡盘台的中心部分中的孔，面朝下的晶片在该孔中是 安装在卡盘工作台的孔下方并安装了摄像机。 在通过照相机正确地对齐晶片并识别晶片正面上形成的半导体芯片形状之后，通过锯片执行晶片切割工艺。