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公开(公告)号：KR1020100053425A
公开(公告)日：2010-05-20
申请号：KR1020090061735
申请日：2009-07-07
Applicant: 삼성전자주식회사
CPC classification number: H01L24/75 , H01L2224/16225
Abstract: PURPOSE: A coil is provided to increase processing speed by reducing the time consumed in the packaging process. CONSTITUTION: A coil(10301) comprises a first body(10320), a second body(10340) and a third body(10360). The first body and the second body have the same shape. The first main body has an upper part(10322) and a lower part(10324). The longitudinal direction of the upper part is generally positioned to be parallel with a first direction(62). The upper part has an inner area and an outer area. The lower part is protruded downward from the upper part in a third direction(66). The lower part has an area which is perpendicular in a third direction and smaller than the upper part. The lower part of the first body and the lower part of the second body face each other.
Abstract translation: 目的：提供线圈，通过减少包装过程中消耗的时间来提高处理速度。 构成：线圈（10301）包括第一主体（10320），第二主体（10340）和第三主体（10360）。 第一体和第二体具有相同的形状。 第一主体具有上部（10322）和下部（10324）。 上部的纵向方向通常定位成与第一方向（62）平行。 上部具有内部区域和外部区域。 下部在第三方向（66）从上部向下突出。 下部具有在第三方向上垂直且小于上部的区域。 第一主体的下部和第二主体的下部彼此面对。
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Patent Agency Ranking2.发明公开칩 패드를 기판 패드에 연결하는 탄성 조인트 및 이를구비하는 반도체 패키지, 그리고 칩 패드를 기판 패드에연결하는 방법 无效用于将芯片垫与衬底垫连接的弹性接头和包括其的半导体封装以及将衬垫与衬底垫连接的方法
公开(公告)号：KR1020080107609A
公开(公告)日：2008-12-11
申请号：KR1020070055574
申请日：2007-06-07
Applicant: 삼성전자주식회사
CPC classification number: H01L2224/16 , H01L2924/00012
Abstract: An elasticity joint connecting the chip pad, a semiconductor package including the same, and a method for connecting the chip pad to the substrate pad are provided to prevent the joint from being damaged by the external force. An elasticity joint(10) connects the chip pad formed on the semiconductor chip(C) to the substrate pad formed on the substrate(S). The elastic body comprises the elastic body which electrically connects the chip pad and the substrate pad. The elasticity joint more includes the upper pad and the bottom pad. One side of the upper pad is adhered to the chip pad. The bottom pad is separated from the upper pad. One side of the bottom pad is adhered to the substrate pad. One end and the other end of the elastic body are respectively connected to the upper pad and bottom pad.
Abstract translation: 提供连接芯片焊盘，包括该芯片焊盘的半导体封装和将芯片焊盘与基板焊盘连接的方法的弹性接头，以防止接头被外力损坏。 弹性接头（10）将形成在半导体芯片（C）上的芯片焊盘连接到形成在基板（S）上的基板焊盘。 弹性体包括将芯片焊盘和衬底焊盘电连接的弹性体。 弹性接头还包括上垫和底垫。 上垫的一侧粘附到芯片垫。 底垫与上垫分开。 底垫的一侧粘附到基板垫。 弹性体的一端和另一端分别连接到上垫和底垫。
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公开(公告)号：KR100825799B1
公开(公告)日：2008-04-29
申请号：KR1020070000681
申请日：2007-01-03
Applicant: 삼성전자주식회사
Inventor： 우현정
IPC: H01L23/28
CPC classification number: H01L23/562 , H01L23/3128 , H01L24/16 , H01L24/28 , H01L24/33 , H01L24/45 , H01L24/48 , H01L24/73 , H01L25/50 , H01L2224/16 , H01L2224/2919 , H01L2224/32057 , H01L2224/32145 , H01L2224/32225 , H01L2224/45139 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/83101 , H01L2224/83385 , H01L2225/0651 , H01L2924/00011 , H01L2924/00014 , H01L2924/01006 , H01L2924/01027 , H01L2924/01033 , H01L2924/01047 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/0665 , H01L2924/00 , H01L2924/3512 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599 , H01L2924/01049
Abstract: A semiconductor chip for depressing voids in a die bonding process and a semiconductor package including the same are provided to prevent the generation of the voids by forming a void prevention path. A semiconductor chip(100) includes a void prevention path(106) which is formed in constant depth on an upper surface thereof. The void prevention path is extended to a scribe line(102). The depth of the void prevention path belongs to a range of 3-10 mum. The void prevention path is formed across a horizontal direction, a vertical direction, or an oblique direction of the semiconductor chip. The void prevention path is formed on a passivation layer which is positioned on a top surface of the semiconductor chip. A coating layer is formed on the passivation layer.
Abstract translation: 提供了一种用于在芯片接合工艺中抑制空隙的半导体芯片和包括该半导体芯片的半导体封装，以通过形成空隙防止路径来防止产生空隙。 半导体芯片（100）包括在其上表面上以恒定深度形成的空隙防止路径（106）。 空隙防止路径延伸到划线（102）。 防漏路径的深度属于3-10μm的范围。 在半导体芯片的水平方向，垂直方向或倾斜方向上形成防漏路径。 空隙防止路径形成在位于半导体芯片的顶表面上的钝化层上。 在钝化层上形成涂层。
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公开(公告)号：KR101560774B1
公开(公告)日：2015-10-16
申请号：KR1020090061735
申请日：2009-07-07
Applicant: 삼성전자주식회사
CPC classification number: H01L24/75 , H01L2224/16225
Abstract: 반도체칩을패키지하는장치가제공된다. 패키지장치는유도가열에의해반도체칩의솔더볼을리플로우하는코일을가진다. 코일은제 1 몸체, 이와나란하게제공되는제 2 몸체, 그리고제 1 몸체로부터제 2 몸체까지연장되는제 3 몸체를가진다. 제 1 몸체와제 2 몸체는이들사이를가로지르는수직평면에대해대칭이되도록제공된다. 제 1 몸체와제 2 몸체는각각서로에대해마주보는면이아래로갈수록서로에대해멀어지도록제공되는경사면을가진다.
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公开(公告)号：KR1020130038582A
公开(公告)日：2013-04-18
申请号：KR1020110103018
申请日：2011-10-10
Applicant: 삼성전자주식회사
CPC classification number: H01L23/642 , G11C11/4074 , H01L2924/0002 , H01L2924/00
Abstract: PURPOSE: A semiconductor chip package including a voltage generating circuit with reduced power noises is provided to improve the reliability of a data access operation by minimizing power noises using a noise canceller. CONSTITUTION: A voltage generating circuit(230) generates a supply voltage for an internal circuit by receiving an external power voltage. An IC chip(200) includes a connection terminal connected to the output node of the supply voltage of the voltage generating circuit. A noise canceller(120) is electrically connected to the connection terminal to cancel power noises from the supply voltage. A mounting substrate mounts the IC chip for packaging the IC chip.
Abstract translation: 目的：提供一种包括具有降低功率噪声的电压产生电路的半导体芯片封装，以通过使用噪声消除器来最小化电力噪声来提高数据访问操作的可靠性。 构成：电压产生电路（230）通过接收外部电源电压来产生内部电路的电源电压。 IC芯片（200）包括连接到电压产生电路的电源电压的输出节点的连接端子。 噪声消除器（120）电连接到连接端子以从电源电压中消除电力噪声。 安装基板安装用于封装IC芯片的IC芯片。
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