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公开(公告)号：KR1020140015169A
公开(公告)日：2014-02-06
申请号：KR1020130011488
申请日：2013-01-31
Applicant: 삼성전자주식회사
IPC: G11C29/08
Abstract: A memory module and a memory test system for testing the same are disclosed. The memory module according to an embodiment of the present invention may include a plurality of ranks and a test control unit wherein the test control unit can be set into a rank parallel test mode. The test control unit set into the rank parallel test mode can activate selected signals which correspond to the ranks simultaneously. The memory test system according to an embodiment of the present invention can test the memory module by recognizing the ranks of the memory module as one rank. [Reference numerals] (AA) No; (BB) Yes; (S01) Power supply; (S02) Rank parallel test mode?; (S03) Control a memory controller in order for a memory module to start the rank parallel test mode; (S04) Recognize the number of ranks included in the memory module as one; (S05,S07) Initialize a system; (S06) Execute a memory module test program
Abstract translation: 公开了一种用于测试它的存储器模块和存储器测试系统。 根据本发明的实施例的存储器模块可以包括多个等级和测试控制单元，其中测试控制单元可以被设置为秩并行测试模式。 设置为等级并行测试模式的测试控制单元可以同时激活与行列相对应的选定信号。 根据本发明的实施例的存储器测试系统可以通过将存储器模块的等级识别为一个等级来测试存储器模块。 （附图标记）（AA）否; （BB）是的; （S01）电源; （S02）等级并行测试模式？ （S03）控制内存控制器，使内存模块启动并行测试模式; （S04）将内存模块中列出的队列数量确认为1; （S05，S07）初始化系统; （S06）执行内存模块测试程序
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公开(公告)号：KR1020090002964A
公开(公告)日：2009-01-09
申请号：KR1020070067404
申请日：2007-07-05
Applicant: 삼성전자주식회사
IPC: G02F1/167
CPC classification number: G02F1/167 , G02F2001/1672 , G02F2001/1678 , G09G3/344
Abstract: A method for manufacturing an electro phoretic display is provided to improve the color property through a color particle which is minutely arranged. A thin film transistor is formed(S11). The micro cup is formed on the top of the thin film transistor(S21). Solvent is charged as a portion within micro cup(S31). The color particle which accelerated flies is arranged to deflector in micro cup(S51). It the micro cup in which the color particle is arranged is charged with solvent with the second(S61). The protection substrate is welded on the top of micro cup(S71).
Abstract translation: 提供了一种用于制造电泳显示器的方法，以通过精细布置的彩色颗粒来改善色彩特性。 形成薄膜晶体管（S11）。 微型杯形成在薄膜晶体管的顶部（S21）。 溶剂作为微杯内的部分（S31）充电。 加速飞行的颜色粒子布置成在微杯中偏转（S51）。 其中排列有彩色颗粒的微杯用第二种（S61）装入溶剂。 将保护基板焊接在微杯的顶部（S71）上。
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公开(公告)号：KR1020080111966A
公开(公告)日：2008-12-24
申请号：KR1020070060579
申请日：2007-06-20
Applicant: 삼성전자주식회사
IPC: G02F1/167 , G02F1/1335
CPC classification number: G02F1/167 , G02F2001/1676 , G02F2001/1678 , G09G3/344
Abstract: A display device is provided to prevent misalign between a first and a second substrate, and mixture of color pixels. Pixel electrodes(130) are formed in a first base substrate. A second base substrate(210) is facing the first base substrate. Color pixels are positioned inside the domain in which the pixel electrode corresponding to is formed. The color pixels are formed on the second base substrate by point-to-point mapping with the pixel electrodes. The color pixels includes a red color pixel(221), a green color pixel(222), and a blue color pixel(223). A common electrode(230) is formed on the second base substrate to cover the color pixels. An electrophoresis layer(300) is interposed between the pixel electrode and the common electrode.
Abstract translation: 提供了一种显示装置，以防止第一和第二基板之间的不对准以及彩色像素的混合。 像素电极（130）形成在第一基底衬底中。 第二基底（210）面向第一基底。 彩色像素位于其中形成有对应的像素电极的域内。 通过与像素电极的点对点映射，在第二基板上形成彩色像素。 彩色像素包括红色像素（221），绿色像素（222）和蓝色像素（223）。 公共电极（230）形成在第二基底基板上以覆盖彩色像素。 在像素电极和公共电极之间插入电泳层（300）。
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公开(公告)号：KR1020080035833A
公开(公告)日：2008-04-24
申请号：KR1020060102387
申请日：2006-10-20
Applicant: 삼성전자주식회사
Abstract: A memory module for testing a plurality of ranks at the same time and a method for testing the same are provided to reduce a time needed for testing an FBDIMM(Fully Buffered Double In-line Memory Module), which includes an AMB(Advanced Memory Buffer) and a plurality of ranks including a plurality of memory chips respectively, by selecting and testing at least two ranks among a plurality of ranks at the same time. Two ranks(200) respectively include a plurality of DRAMs. An AMB(100) selects/tests at least two ranks at the same time based on packet information received from a motherboard chipset and configuration information received from a system management bus. The AMB includes a decoding block(110) outputting first rank selection signals by de-serializing/decoding the received packet information, a configuration register block(120) outputting a rank selection control signal based on the received configuration information, a rank selection circuit(130) outputting second rank selection signals for selecting at least one rank based on the first rank selection signals and the rank selection control signal, and buffers(140-150) respectively buffering the rank selection signal corresponding to the second rank selection signal to the corresponding rank.
Abstract translation: 提供了用于同时测试多个等级的存储器模块和用于测试其的方法，以减少测试FBDIMM（全缓冲双列直插存储器模块）所需的时间，该FBDIMM（全缓冲双列直插式存储器模块）包括AMB（高级存储器缓冲器 ）和分别包括多个存储器芯片的多个等级，通过同时选择和测试多个等级中的至少两个等级。 两级（200）分别包括多个DRAM。 AMB（100）基于从主板芯片组接收的分组信息和从系统管理总线接收的配置信息同时选择/测试至少两个等级。 AMB包括通过对接收到的分组信息进行解串行/解码来输出第一等级选择信号的解码块（110），基于接收的配置信息输出等级选择控制信号的配置寄存器块（120），等级选择电路 130）输出用于基于第一等级选择信号和等级选择控制信号选择至少一个等级的第二等级选择信号，以及分别缓冲对应于第二等级选择信号的等级选择信号的缓冲器（140-150） 秩。
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公开(公告)号：KR1020060107092A
公开(公告)日：2006-10-13
申请号：KR1020050029093
申请日：2005-04-07
Applicant: 삼성전자주식회사
Abstract: 메모리 모듈의 테스트 장치가 제공된다. 메모리 모듈의 테스트 장치는 피테스트 메모리 모듈의 정보가 저장된 제1 메모리부를 구비하는 피테스트 메모리 모듈이 장착되는 테스트 슬롯, 칩셋에서 인식 가능한 메모리 모듈에 관한 정보가 저장된 제2 메모리부, 구동 신호를 제1 및 제2 메모리부에 선택적으로 전달하는 제1 스위칭부를 포함한다.
메모리 모듈, 테스트, SPD, DIMM, SODIMM-
Patent Agency Ranking
公开(公告)号：KR1020090096154A
公开(公告)日：2009-09-10
申请号：KR1020080021566
申请日：2008-03-07
Applicant: 삼성전자주식회사
IPC: G11C29/00
CPC classification number: G11C29/26 , G11C5/04 , G11C2029/2602 , G11C29/10 , G11C29/20 , G11C2029/3602
Abstract: A test system capable of performing a parallel bit test is provided to reduce probability of error generation in a parallel bit test about a plurality of memory modules. A plurality of counters(330,340) counts the number of output signals having the same logic state among output signals of each memory module, and outputs a count signal. The counter outputs a count signal having a different logic state according to odd number or even number of the output signals having the same logic state. A comparing part(350) compares the count signal outputted in each counter, and outputs a comparing signal corresponding to a defect of the memory module. A control part(360) controls an enable state of the memory module in response to the comparing signal. The control part controls application of a DQS signal in a pad in response to the comparing signal.
Abstract translation: 提供能够执行并行比特测试的测试系统，以减少关于多个存储器模块的并行比特测试中的错误产生的概率。 多个计数器（330,340）对每个存储器模块的输出信号中具有相同逻辑状态的输出信号的数量进行计数，并输出计数信号。 计数器根据具有相同逻辑状态的输出信号的奇数或偶数输出具有不同逻辑状态的计数信号。 比较部分（350）比较在每个计数器中输出的计数信号，并输出与存储器模块的缺陷相对应的比较信号。 控制部分（360）响应于比较信号控制存储器模块的使能状态。 控制部分响应于比较信号来控制在焊盘中的DQS信号的应用。
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公开(公告)号：KR1020080006749A
公开(公告)日：2008-01-17
申请号：KR1020060065868
申请日：2006-07-13
Applicant: 삼성전자주식회사
IPC: G06F11/28
CPC classification number: G11C29/56 , G01R31/318505 , G01R31/318513 , G11C5/04 , G11C29/56012 , G11C2029/5602
Abstract: A system for mounting and testing a memory module is provided to reduce a test time by mounting a plurality of memory modules to a plurality of test slots at the same time, and test a fast UDIMM(Unbuffered Double In-line Memory Module) by using an RDIMM(Registered Double In-Line Memory Module) or FBDIMM(Fully Buffered Double In-Line Memory Module) server system. A motherboard(31) is equipped with at least one module socket(SL1-A,SL1-B,SL2-A,SL2-B). A test board(33) is equipped with at least one test socket for receiving a memory module in a mounting test. A connecting unit connects the motherboard and the test board electrically. A PLL(Phase Locked Loop)/register(35) is mounted on the test board to correct property of signals. The connecting unit includes interface sockets(36,37) arranged to one side of the test board, and interface boards(38,39) inserted between the interface socket and the module socket. The connecting unit is at least one of a connector, an FPCB(Flexible Printed Circuit Board), and a conductive iron core. The module socket supports an RDIMM interface and the test socket supports a UDIMM interface.
Abstract translation: 提供了一种用于安装和测试存储器模块的系统，以通过将多个存储器模块同时安装到多个测试槽来减少测试时间，并且通过使用快速UDIMM（无缓冲双列直插式存储器模块）来测试 RDIMM（注册双列直插内存模块）或FBDIMM（全缓冲双列直插内存模块）服务器系统。 主板（31）配备有至少一个模块插座（SL1-A，SL1-B，SL2-A，SL2-B）。 测试板（33）配备有至少一个用于在安装测试中接收存储器模块的测试插座。 连接单元电连接主板和测试板。 PLL（锁相环）/寄存器（35）安装在测试板上，以校正信号的性质。 连接单元包括布置在测试板一侧的接口插座（36,37）和插入接口插座和模块插座之间的接口板（38,39）。 连接单元是连接器，FPCB（柔性印刷电路板）和导电铁芯中的至少一个。 模块插槽支持RDIMM接口，测试插座支持UDIMM接口。
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公开(公告)号：KR1020070062633A
公开(公告)日：2007-06-18
申请号：KR1020050122252
申请日：2005-12-13
Applicant: 삼성전자주식회사
IPC: G06F1/16
Abstract: An interface socket device mounted to a system board of a computer system is provided to prevent physical damage of a system module socket arranged to the system board and reduce time required for testing a memory module by being mounted to the memory module socket. An interface PCB(Printed Circuit Board)(300) includes the first and second surface(310,320), and circuit patterns. Two interface module sockets(400A,400B) are arranged to the first surface and are electrically connected to the interface PCB through the circuit patterns. A connection PCB(500) is formed under the second surface and is electrically connected to the interface module sockets through the circuit patterns. The connection PCB is mounted to the memory module socket. A buffer circuit(510) is formed on the connection PCB and is electrically connected to a memory controller through a chip select line. The buffer circuit buffers a chip select signal received from the memory controller and provides the buffered chip select signal to each interface module socket through the circuit patterns.
Abstract translation: 提供安装到计算机系统的系统板的接口插座装置，以防止布置在系统板上的系统模块插座的物理损坏，并减少通过安装到存储器模块插座来测试存储器模块所需的时间。 接口PCB（印刷电路板）（300）包括第一和第二表面（310,320）和电路图案。 两个接口模块插座（400A，400B）被布置到第一表面并且通过电路图案电连接到接口PCB。 连接PCB（500）形成在第二表面下方并且通过电路图案电连接到接口模块插座。 连接PCB安装到内存模块插槽。 缓冲电路（510）形成在连接PCB上，并通过芯片选择线与存储器控制器电连接。 缓冲电路缓冲从存储器控制器接收到的芯片选择信号，并通过电路图案将缓冲的芯片选择信号提供给每个接口模块插座。
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公开(公告)号：KR100703969B1
公开(公告)日：2007-04-06
申请号：KR1020050029093
申请日：2005-04-07
Applicant: 삼성전자주식회사
Abstract: 메모리 모듈의 테스트 장치가 제공된다. 메모리 모듈의 테스트 장치는 피테스트 메모리 모듈의 정보가 저장된 제1 메모리부를 구비하는 피테스트 메모리 모듈이 장착되는 테스트 슬롯, 칩셋에서 인식 가능한 메모리 모듈에 관한 정보가 저장된 제2 메모리부, 구동 신호를 제1 및 제2 메모리부에 선택적으로 전달하는 제1 스위칭부를 포함한다.
메모리 모듈, 테스트, SPD, DIMM, SODIMM-
公开(公告)号：KR100576176B1
公开(公告)日：2006-05-03
申请号：KR1020040038823
申请日：2004-05-31
Applicant: 삼성전자주식회사
IPC: G01R31/319 , G01R31/3187 , G01R31/26
Abstract: 반도체 메모리 장치를 실장 상태에서 테스트 할 수 있는 테스트 장치 및 방법이 개시된다. n(2≤n)개의 칩선택단자들을 가진 피측정용 메모리 모듈이 삽입되는 제1슬롯, 시리얼 불휘발성 메모리만 장착된 더미 메모리 모듈이 각각 삽입되는 하나 이상의 제2슬롯들, m(1≤m
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