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公开(公告)号：KR101581431B1
公开(公告)日：2015-12-30
申请号：KR1020090083632
申请日：2009-09-04
Applicant: 삼성전자주식회사
IPC: H01L21/301
CPC classification number: H01L21/78 , H01L23/562 , H01L23/585 , H01L2924/0002 , H01L2924/00
Abstract: 가드링을갖는반도체칩이제공된다. 상기반도체칩은메인칩 영역및 상기메인칩 영역을둘러싸는스크라이브레인영역을구비하는반도체기판을구비한다. 상기반도체기판상에절연막이배치되고, 상기스크라이브레인영역내의상기절연막내에가드링이배치된다. 상기가드링은상기메인칩 영역의적어도일 부분을둘러싼다. 상기가드링은상기절연막의취성(brittleness)보다큰 취성을갖는다. 상기반도체칩의제조방법또한제공된다.
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公开(公告)号：KR1020140039846A
公开(公告)日：2014-04-02
申请号：KR1020120106600
申请日：2012-09-25
Applicant: 삼성전자주식회사
IPC: H01L23/36
CPC classification number: H01L29/34 , H01L21/563 , H01L21/565 , H01L23/3128 , H01L23/34 , H01L23/3675 , H01L23/42 , H01L23/4334 , H01L23/49811 , H01L24/97 , H01L25/105 , H01L29/1033 , H01L2224/16225 , H01L2224/32225 , H01L2224/45139 , H01L2224/48095 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2224/97 , H01L2225/1023 , H01L2225/1058 , H01L2225/1076 , H01L2225/1094 , H01L2924/10271 , H01L2924/15174 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
Abstract: Provided is a semiconductor package including a housing which includes a first package substrate; a first semiconductor chip which is arranged on the first package substrate; a heat transmission layer which is arranged on the first semiconductor chip; a heat spreader which is arranged on the heat transmission layer; a molding part which is arranged on the first package substrate and directly surrounds the lateral surfaces of the first semiconductor chip; and a guide wall which is arranged on the molding part and indirectly surrounds the peripheral part of the heat spreader.
Abstract translation: 提供一种半导体封装，包括：壳体，其包括第一封装基板; 布置在第一封装基板上的第一半导体芯片; 布置在第一半导体芯片上的传热层; 布置在传热层上的散热器; 模制部件，其布置在所述第一封装基板上并且直接围绕所述第一半导体芯片的侧表面; 以及引导壁，其设置在成型部件上并间接地包围散热器的周边部分。
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公开(公告)号：KR1020100020809A
公开(公告)日：2010-02-23
申请号：KR1020080079573
申请日：2008-08-13
Applicant: 삼성전자주식회사
IPC: H01L23/12
CPC classification number: H01L25/105 , H01L23/49816 , H01L23/5387 , H01L24/48 , H01L25/0657 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2225/1064 , H01L2924/00014 , H01L2924/181 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: PURPOSE: A semiconductor package and a method for manufacturing the same are provided to implement an ultra thin and small structure since there is no need an interposer between laminated packages. CONSTITUTION: A semiconductor package(100) comprises a first package(110) and a second package(120). The first package mounts the first semiconductor chip(112) in a first substrate(114). The second package mounts the second semiconductor chip(122) in a second substrate(124). The second substrate is bent to cover the side of the first package and is contacted with the first substrate. The second package is electrically connected to the first package. One among the first and the second substrates comprise the connection pad(114a). A connection terminal touches with the connection pad.
Abstract translation: 目的：提供半导体封装及其制造方法以实现超薄和小结构，因为不需要层叠封装之间的插入件。 构成：半导体封装（100）包括第一封装（110）和第二封装（120）。 第一封装将第一半导体芯片（112）安装在第一衬底（114）中。 第二封装将第二半导体芯片（122）安装在第二衬底（124）中。 第二基板弯曲以覆盖第一封装的侧面并与第一基板接触。 第二封装电连接到第一封装。 第一和第二基板之一包括连接垫（114a）。 连接端子与连接板接触。
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公开(公告)号：KR1020070052837A
公开(公告)日：2007-05-23
申请号：KR1020050110574
申请日：2005-11-18
Applicant: 삼성전자주식회사
Inventor： 이정도
Abstract: 본 발명은 광대역 부호 분할 다중접속 시스템 기지국의 시스템 클럭 최소화 방법에 관한 것으로, 시스템 클럭을 최소화하는 기지국에 있어서, 시스템 클럭 동기화 이벤트가 발생하면, 기지국 프레임 넘버(BTS Frame number : BFN), chipx8의 클럭을 포함한 시스템 클럭을 수신하여 상기 기지국 프레임 넘버(BFN)의 데이터 존재 여부를 확인하기 위하여 데이터 비트 체인지의 발생을 검사하고, 상기 검사결과, 데이터 비트 체인지가 발생하지 않으면, 클럭 카운터를 증가시키고 상기 카운터의 누적 카운터가 미리 정한 값보다 큰 값인지 검사하고, 상기 검사결과, 상기 누적 카운터가 미리 정한 값보다 큰 값이면, 상기 기지국 프레임 넘버(BFN)의 첫번째 프레임을 검사하는 프레임 비트 체인지의 발생을 검사하고, 상기 검사결과, 프레임 비트 체인지가 발생하여 상기 첫 번째 프레임으로 확인하면, 10ms의 프레임 신호를 발생하는 프레임 생성기를 포함하는 시스템 클럭을 최소화하는 기지국에 관한 것이다.
클럭주파수, chipx8, 채널카드, WCDMA, BTS SYSTEM CLOCK-
公开(公告)号：KR1020140029826A
公开(公告)日：2014-03-11
申请号：KR1020120095590
申请日：2012-08-30
Applicant: 삼성전자주식회사
IPC: H01L23/367
CPC classification number: H01L23/34 , H01L23/3128 , H01L23/3142 , H01L23/367 , H01L23/42 , H01L23/4334 , H01L23/49827 , H01L25/0652 , H01L2224/13025 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2224/73253 , H01L2225/06513 , H01L2225/06541 , H01L2225/06589 , H01L2924/15311 , H01L2924/18161
Abstract: The present invention relates to a semiconductor package and a method for manufacturing the same. The semiconductor package includes: a semiconductor chip which is mounted on a substrate; a molding part which protects the semiconductor chip and has an upper surface with a height equal to the height of the upper surface of the semiconductor chip; a heat radiation part which is arranged on the semiconductor chip and the molding part; and a bonding part which is placed among the molding part, the semiconductor chip and the heat radiation part. An interface between the heat radiation part and the bonding part has a convex-concave structure.
Abstract translation: 半导体封装及其制造方法技术领域本发明涉及半导体封装及其制造方法。 半导体封装包括：安装在基板上的半导体芯片; 保护半导体芯片并具有高度等于半导体芯片的上表面的高度的上表面的模制部件; 布置在半导体芯片和模制部件上的散热部分; 以及配置在成型部，半导体芯片和散热部之间的接合部。 散热部与接合部之间的界面具有凸凹结构。
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Patent Agency Ranking
公开(公告)号：KR1020130089115A
公开(公告)日：2013-08-09
申请号：KR1020120010520
申请日：2012-02-01
Applicant: 삼성전자주식회사
IPC: H01L23/36
CPC classification number: H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2924/15311 , H01L2924/00
Abstract: PURPOSE: A semiconductor device having a heat spreader is provided to minimize the distortion of a mounting substrate due to temperature rise by using the heat spreader consisting of upper and lower metal layers which have different coefficients of thermal expansion. CONSTITUTION: A semiconductor chip (140) is formed on a mounting substrate (120). The mounting substrate includes solder balls (110) arranged in a grid pattern. A heat radiation material layer (160) covers the upper surface of the semiconductor chip. A heat radiation member (170) covers the heat radiation material layer and is adhered to the mounting substrate. The heat radiation member includes a lower metal layer (170a) having a first thermal coefficient of expansion and an upper metal layer (170b) having a second coefficient of thermal expansion.
Abstract translation: 目的：提供具有散热器的半导体器件，以通过使用具有不同热膨胀系数的上金属层和下金属层构成的散热器，由于温度上升而使安装基板的变形最小化。 构成：半导体芯片（140）形成在安装基板（120）上。 安装基板包括以网格图案布置的焊球（110）。 散热材料层（160）覆盖半导体芯片的上表面。 散热构件（170）覆盖散热材料层并粘附到安装基板。 散热构件包括具有第一热膨胀系数的下金属层（170a）和具有第二热膨胀系数的上金属层（170b）。
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公开(公告)号：KR1020090033605A
公开(公告)日：2009-04-06
申请号：KR1020070098705
申请日：2007-10-01
Applicant: 삼성전자주식회사
IPC: H01L23/12
CPC classification number: H01L25/105 , H01L24/73 , H01L25/0655 , H01L25/50 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/15311 , H01L2924/3511 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
Abstract: A stack-type semiconductor package, method of forming the same and electronic system including the same are provided to improve the degree of integration by connecting the lower part chip package and top chip package electrically through both sides adhesion wiring board. The lower printed circuit board(100) comprises a plurality of wirings(100a) and plurality of bump(100b) for the bonds. One or a plurality of first underlying chips(105) is laminated successively on the lower printed circuit board. First underlying chips are electrically connected with a plurality of wirings. The first underlying chips is covered with the lower shaping resin compound(108). The top chip package(115) is adhered at both sides adhesion wiring board.
Abstract translation: 提供堆叠型半导体封装，其形成方法和包括该堆叠型半导体封装的电子系统，以通过两侧粘着布线板电连接下部芯片封装和顶部芯片封装来提高集成度。 下部印刷电路板（100）包括多个布线（100a）和用于该键的多个凸起（100b）。 一个或多个第一底层芯片（105）依次层叠在下部印刷电路板上。 第一底层芯片与多条布线电连接。 第一底层芯片被下形成树脂化合物（108）覆盖。 顶片封装（115）在两侧粘附线路板上粘合。
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公开(公告)号：KR1020130105175A
公开(公告)日：2013-09-25
申请号：KR1020120027383
申请日：2012-03-16
Applicant: 삼성전자주식회사
CPC classification number: H01L23/36 , H01L21/563 , H01L23/3128 , H01L23/3157 , H01L23/4334 , H01L23/49816 , H01L23/49827 , H01L24/16 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L25/105 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/73253 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/06562 , H01L2225/1023 , H01L2225/1058 , H01L2924/00013 , H01L2924/00014 , H01L2924/15184 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H01L2924/00012 , H01L2224/13099 , H01L2224/05099 , H01L2224/05599 , H01L2924/014 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: PURPOSE: A semiconductor package having a protection layer and a method for forming the same are provided to easily release heat generated from a chip by using a flip chip package. CONSTITUTION: A first semiconductor chip (41) is formed on a first substrate. A protection layer (31) is formed on the first semiconductor chip. An encapsulating material (47) covers the first substrate. The encapsulating material is in contact with the lateral surface of the first semiconductor chip and the lateral surface of the protection layer. The protection layer is in direct contact with the first semiconductor chip.
Abstract translation: 目的：提供具有保护层的半导体封装及其形成方法，以便通过使用倒装芯片封装容易地释放从芯片产生的热量。 构成：第一半导体芯片（41）形成在第一基板上。 在第一半导体芯片上形成保护层（31）。 封装材料（47）覆盖第一基板。 封装材料与第一半导体芯片的侧表面和保护层的侧表面接触。 保护层与第一半导体芯片直接接触。
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公开(公告)号：KR1020110025526A
公开(公告)日：2011-03-10
申请号：KR1020090083632
申请日：2009-09-04
Applicant: 삼성전자주식회사
IPC: H01L21/301
CPC classification number: H01L21/78 , H01L23/562 , H01L23/585 , H01L2924/0002 , H01L2924/00
Abstract: PURPOSE: A semiconductor chips and a manufacturing method thereof are provided to improve the reliability of an integrated circuit by preventing the generation of the crack within the insulation layers. CONSTITUTION: A semiconductor substrate(10) comprises a main chip area and a scribe lane area that surrounds the main chip area. An insulating layer(31) is arranged on the semiconductor substrate. A guard ring(34) is formed within the insulating layer within the scribe lane area. The guard ring surrounds at least a part of the main chip area.
Abstract translation: 目的：提供半导体芯片及其制造方法，以通过防止在绝缘层内产生裂纹来提高集成电路的可靠性。 构成：半导体衬底（10）包括主芯片区域和围绕主芯片区域的划线通道区域。 绝缘层（31）布置在半导体衬底上。 保护环（34）形成在划线区域内的绝缘层内。 保护环围绕主芯片区域的至少一部分。
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