公开(公告)号：KR1020120135626A

公开(公告)日：2012-12-17

申请号：KR1020110054444

申请日：2011-06-07

Applicant: 삼성전자주식회사

Inventor： 변학균 ,  심종보 ,  이우동 ,  도래형 ,  김부원

IPC: H01L23/48 ,  H01L23/12

CPC classification number: H01L21/784 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/3178 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/80 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02371 ,  H01L2224/03009 ,  H01L2224/0332 ,  H01L2224/0345 ,  H01L2224/0362 ,  H01L2224/03622 ,  H01L2224/03903 ,  H01L2224/05018 ,  H01L2224/05027 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05558 ,  H01L2224/05564 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/0566 ,  H01L2224/06135 ,  H01L2224/08145 ,  H01L2224/08148 ,  H01L2224/08155 ,  H01L2224/27009 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/32145 ,  H01L2224/33181 ,  H01L2224/80815 ,  H01L2224/83191 ,  H01L2224/83193 ,  H01L2224/94 ,  H01L2225/06551 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/1441 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2224/03 ,  H01L2924/01028 ,  H01L2224/27 ,  H01L2924/00 ,  H01L2224/05552

Abstract: PURPOSE: A method for manufacturing a semiconductor chip package is provided to solder connection patterns by laminating semiconductor chips and to electrically connect the semiconductor chips with the connection patterns, thereby reducing the size of the semiconductor chip package. CONSTITUTION: A semiconductor substrate(10) has a front side and a rear side which is faced with the front side. A chip pad is formed on the front side of the semiconductor substrate. A connection pattern(120) covers a sidewall of the semiconductor substrate. Connection patterns of semiconductor chips(100) are soldered and connect the laminated semiconductor chips. A sidewall part is extended from a first contact part and covers the sidewall of the semiconductor substrate.

Abstract translation: 目的：提供一种制造半导体芯片封装的方法，通过层叠半导体芯片来焊接连接图案，并将半导体芯片与连接图案电连接，从而减小半导体芯片封装的尺寸。 构成：半导体衬底（10）具有面向前侧的前侧和后侧。 在半导体基板的前侧形成有芯片焊盘。 连接图案（120）覆盖半导体衬底的侧壁。 半导体芯片（100）的连接图案被焊接并连接层叠半导体芯片。 侧壁部分从第一接触部分延伸并且覆盖半导体衬底的侧壁。

公开(公告)号：KR1020090025908A

公开(公告)日：2009-03-11

申请号：KR1020070091099

申请日：2007-09-07

Applicant: 삼성전자주식회사

Inventor： 이정도 ,  변학균 ,  김태훈 ,  한상욱 ,  유선향

IPC: H01L23/12

CPC classification number: H01L25/50 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L25/03 ,  H01L25/105 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/18165 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H05K1/181 ,  Y10T29/49169 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An electronic device and a formation method having a stacked semiconductor package are provided to decrease the total thickness by positioning the upper chip structure of the semiconductor package within the depressed region of the lower part semiconductor package. An electronic device having a stacked semiconductor package comprises a lower substrate(100); an underlying chip structure formed on the lower substrate; a lower part electronic component including the lower molding film(109) having a depressed region(109a) in the upper side; an upper substrate(200) formed on the lower part electronic component; an upper electronic component including the upper chip structure protruded from the upper substrate in order to be located within the depressed region.

Abstract translation: 提供具有堆叠半导体封装的电子器件和形成方法，以通过将半导体封装的上部芯片结构定位在下部半导体封装的凹陷区域内来减小总厚度。 具有层叠半导体封装的电子器件包括下基板（100）; 形成在下基板上的底层芯片结构; 下部电子部件，其具有在上侧具有凹陷区域（109a）的下部成型膜（109） 形成在下部电子部件上的上基板（200） 上部电子部件，其包括从上部基板突出的上部芯片结构，以位于凹陷区域内。

公开(公告)号：KR100817075B1

公开(公告)日：2008-03-26

申请号：KR1020060110538

申请日：2006-11-09

Applicant: 삼성전자주식회사

Inventor： 변학균 ,  조태제 ,  심종보 ,  한상욱

IPC: H01L23/12

CPC classification number: H01L23/3128 ,  H01L23/12 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A multistack package is provided to eliminate the necessity of an additional carrier frame for supporting a thin substrate in respectively fabricating first and second packages by reducing the total thickness of a multistack package without decreasing the thickness of each package. A first opening(120h) is formed in a predetermined position of a first package(102) including a first substrate(120) and a first semiconductor chip. The first substrate has first and second surfaces(120a,120b). The first semiconductor chip is fixed to a position on the first surface of the first substrate, electrically connected to the first substrate. A second package(104) is electrically connected to the first substrate, including a second substrate(140) and a second semiconductor chip. The second substrate has third and fourth surfaces(140a,140b). The second semiconductor chip is inserted into the first opening, fixed to a position on the third surface of the second substrate while being electrically connected to the second substrate. A joint(170,180) is formed between the second surface of the first substrate and the third surface of the second substrate in the periphery of the first opening to electrically connect the first and second packages. The second semiconductor chip can be inserted into the first opening, sealed by a sealing material(168).

Abstract translation: 提供了一种多级封装以消除额外的载体框架，用于通过在不减小每个封装的厚度的情况下减少多层封装的总厚度来分别制造第一和第二封装来支撑薄的衬底。 第一开口（120h）形成在包括第一基板（120）和第一半导体芯片的第一封装（102）的预定位置。 第一基板具有第一和第二表面（120a，120b）。 第一半导体芯片被固定到第一基板的第一表面上的与第一基板电连接的位置。 第二封装（104）电连接到第一衬底，包括第二衬底（140）和第二半导体芯片。 第二基板具有第三和第四表面（140a，140b）。 第二半导体芯片被插入到第一开口中，固定到第二基板的第三表面上的位置，同时与第二基板电连接。 在第一基板的第二表面和第二基板的第三表面之间，在第一开口的周边形成接头（170,180），以电连接第一和第二封装。 第二半导体芯片可以插入第一开口中，由密封材料（168）密封。

公开(公告)号：KR1020070048953A

公开(公告)日：2007-05-10

申请号：KR1020050106069

申请日：2005-11-07

Applicant: 삼성전자주식회사

Inventor： 권흥규 ,  변학균 ,  김세년 ,  김태훈 ,  하정오

IPC: H01L21/56 ,  H01L23/28

CPC classification number: H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: 본 발명은 반도체 패키지의 게이트 버어(gate burr) 제거 방법에 관한 것으로, 탑 게이트 몰딩(top gate molding) 방법으로 수지 봉합부가 형성되는 반도체 패키지의 경우 수지 봉합부의 상부면에 게이트 버어가 잔존할 수 있다. 이 게이트 버어가 잔존하는 반도체 패키지를 하부 패키지로 사용하여 상부 패키지를 적층할 경우 게이트 버어로 인해 상부 패키지의 솔더 조인트(solder joint) 신뢰성이 떨어진다.
본 발명은 상기한 문제점을 해소하기 위해서, 수지 봉합부의 상부면에 잔존하는 게이트 버어 크기를 체크한 후, 체크된 정보를 바탕으로 설정된 레이저빔(laser beam)을 게이트 버어에 조사(照射)하여 제거하는 반도체 패키지의 게이트 버어 제거 방법을 제공한다. 특히 게이트 버어 제거 단계는 기존의 레이저 마킹(laser marking) 공정에서 함께 진행함으로써, 게이트 버어 제거를 위한 별도의 설비를 구비할 필요가 없고, 게이트 버어 제거 단계로 인한 반도체 패키지 제조 공정 시간이 길어지는 문제를 최소화할 수 있다.
탑 게이트 몰딩, 게이트 버어, 솔더 조인트, 적층, 멀티

公开(公告)号：KR100690922B1

公开(公告)日：2007-03-09

申请号：KR1020050078863

申请日：2005-08-26

Applicant: 삼성전자주식회사

Inventor： 권흥규 ,  김세년 ,  김태훈 ,  하정오 ,  변학균 ,  박성용

IPC: H01L23/12

CPC classification number: H01L23/50 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/85 ,  H01L25/0657 ,  H01L2224/05553 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06572 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Disclosed is a semiconductor device packaging technique that is capable of resolving a problem of instability of bonding wires when stacking a plurality of semiconductor chips. The technique is also capable of realizing a slim, light and small package. The semiconductor device package includes a substrate having a substrate pad on a surface thereof, one or more memory chips stacked on the substrate with each memory chip having a pad connected to a common pin receiving a common signal applied to all the memory chips, an interposer chip stacked on the substrate and having an interconnection wire connected to the memory chip pad, the common pin of each of the memory chips being electrically connected to the interconnection wire via the memory chip pad, and a logic chip stacked on the substrate and having a bypass circuit which electrically connects or disconnects the interconnection wire to or from the substrate pad.

公开(公告)号：KR101719630B1

公开(公告)日：2017-04-04

申请号：KR1020100131508

申请日：2010-12-21

Applicant: 삼성전자주식회사

Inventor： 변학균 ,  최대영 ,  김미연

IPC: H01L23/31 ,  H01L23/48 ,  H01L25/10 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49827 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17179 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: 반도체패키지및 그를포함하는패키지온 패키기가제공된다. 본발명의일 실시예에따른반도체패키지는, 기판, 기판상면에부착된반도체칩, 기판의상면에배치된복수의연결도전체, 기판상에형성되어복수의연결도전체및 반도체칩을매립하는몰딩재, 및몰딩재를관통하여복수의연결도전체를각각노출시키는복수의연결비아홀을포함하되, 복수의연결비아홀 중적어도하나의제1 연결비아홀에대하여, 제1 연결비아홀에의해노출되는제1 연결도전체로부터제1 연결비아홀의입구까지의평면거리가균일하지않다.

Abstract translation: 提供了一种半导体封装和包括该封装的封装。 根据本发明的一个实施例的半导体封装，包括基板，附连到顶部表面的半导体芯片，形成在整个衬底上的多个放置在衬底的上表面上的连接将要被嵌入到一个整体和半导体芯片的多个连接 的模制材料，并且所述模制材料中的多个穿过图的连接，但包括多个导通孔连接，用于分别露出一个整体，，即使多个通，用于经由孔所述第一连接中的一个，所述曝光通过经由孔所述第一连接孔普遍连接 从整个连接图到第一连接通孔入口的1平面距离不均匀。

公开(公告)号：KR1020140042462A

公开(公告)日：2014-04-07

申请号：KR1020120109258

申请日：2012-09-28

Applicant: 삼성전자주식회사

Inventor： 유혜정 ,  변학균 ,  나경태 ,  한승헌 ,  박태성 ,  임충빈

IPC: H01L23/488 ,  H01L23/28

CPC classification number: H01L24/14 ,  H01L23/145 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The present invention relates to a semiconductor package apparatus. The semiconductor package apparatus of the present invention includes a first semiconductor package which includes a first substrate, a solder resist layer which is installed in the first substrate, and a first sealing material which covers and protects the solder resist layer; and solder balls which include a first solder ball which is installed on the first substrate and has a first height, and a second solder ball which has a second height which is different from the first height. The first sealing material may include a perforation hole which is perforated in order to expose the solder balls.

Abstract translation: 本发明涉及一种半导体封装装置。 本发明的半导体封装装置包括第一半导体封装，其包括第一基板，安装在第一基板中的阻焊层，以及覆盖并保护阻焊层的第一密封材料; 以及焊球，其包括安装在第一基板上并具有第一高度的第一焊球，以及具有与第一高度不同的第二高度的第二焊球。 第一密封材料可以包括穿孔以便露出焊球的穿孔。

公开(公告)号：KR1020090033605A

公开(公告)日：2009-04-06

申请号：KR1020070098705

申请日：2007-10-01

Applicant: 삼성전자주식회사

Inventor： 변학균 ,  김태훈 ,  한상욱 ,  이정도 ,  유선향

IPC: H01L23/12

CPC classification number: H01L25/105 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A stack-type semiconductor package, method of forming the same and electronic system including the same are provided to improve the degree of integration by connecting the lower part chip package and top chip package electrically through both sides adhesion wiring board. The lower printed circuit board(100) comprises a plurality of wirings(100a) and plurality of bump(100b) for the bonds. One or a plurality of first underlying chips(105) is laminated successively on the lower printed circuit board. First underlying chips are electrically connected with a plurality of wirings. The first underlying chips is covered with the lower shaping resin compound(108). The top chip package(115) is adhered at both sides adhesion wiring board.

Abstract translation: 提供堆叠型半导体封装，其形成方法和包括该堆叠型半导体封装的电子系统，以通过两侧粘着布线板电连接下部芯片封装和顶部芯片封装来提高集成度。 下部印刷电路板（100）包括多个布线（100a）和用于该键的多个凸起（100b）。 一个或多个第一底层芯片（105）依次层叠在下部印刷电路板上。 第一底层芯片与多条布线电连接。 第一底层芯片被下形成树脂化合物（108）覆盖。 顶片封装（115）在两侧粘附线路板上粘合。

公开(公告)号：KR1020070073187A

公开(公告)日：2007-07-10

申请号：KR1020060000794

申请日：2006-01-04

Applicant: 삼성전자주식회사

Inventor： 김태훈 ,  변학균 ,  박성용 ,  권흥규

IPC: H01L21/60

CPC classification number: H05K3/3436 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/562 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H05K2201/09781 ,  Y02P70/613 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/4554

Abstract: A circuit board, a semiconductor package with the same and a stacked package using the same are provided to improve the reliability of solder bonding and the reliability of a board level by increasing a contact area between an outer ball pad and a solder ball using a relatively large sized outer ball pad structure. A circuit board includes a substrate body(10) with upper and lower surfaces, a resin sealing region(13) for mounting a semiconductor chip on the upper surface of the substrate body, and a metal line layer. The metal line layer is formed in the resin sealing region. The metal line layer includes a bonding pad for contacting electrically the chip, an upper ball pad at a periphery of the resin sealing region and a lower ball pad on the lower surface of the substrate body. The lower ball pad is composed of an inner ball pad and an outer ball pad. The outer ball pad is composed of a first outer ball pad(28) and a second outer ball pad(29). The size of the second outer ball pad is relatively large compared to that of the first outer ball pad.

Abstract translation: 提供电路板，具有该电路板的半导体封装和使用该电路板的堆叠封装，以通过使用相对的方式增加外部球垫和焊球之间的接触面积来提高焊接的可靠性和板级的可靠性 大尺寸外球垫结构。 电路板包括具有上表面和下表面的基板本体（10），用于将半导体芯片安装在基板主体的上表面上的树脂密封区域（13）和金属线层。 金属线层形成在树脂密封区域中。 金属线层包括用于与芯片电接触的接合焊盘，在树脂密封区域周围的上部焊盘和在基板主体的下表面上的下部焊盘。 下球垫由内球垫和外球垫构成。 外球垫由第一外球垫（28）和第二外球垫（29）构成。 与第一外球垫相比，第二外球垫的尺寸相对较大。

公开(公告)号：KR1020130043408A

公开(公告)日：2013-04-30

申请号：KR1020110107513

申请日：2011-10-20

Applicant: 삼성전자주식회사

Inventor： 변학균 ,  정은희 ,  심종보 ,  이우동 ,  염근대

IPC: H01L23/32 ,  H01L23/12

CPC classification number: H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L25/074 ,  H01L23/31 ,  H01L23/32 ,  H01L23/3735 ,  H01L24/42

Abstract: PURPOSE: A multichip package is provided to rapidly discharge high heat to the outside by exposing the upper side of a support member from a molding member. CONSTITUTION: A plurality of semiconductor chips(120) are laminated on a package substrate with a step type. Conductive connection members(140) electrically connect the semiconductor chips to the package substrate. A support member(130) supports the semiconductor chips. A molding member(150) is formed on the upper side of the package substrate. The molding member covers the semiconductor chips, the conductive connection members, and the support member.

Abstract translation: 目的：提供一种多芯片封装，用于通过将支撑构件的上侧从模制构件暴露出来，将高热量快速排出到外部。 构成：多个半导体芯片（120）层叠在具有台阶型的封装基板上。 导电连接构件（140）将半导体芯片电连接到封装衬底。 支撑构件（130）支撑半导体芯片。 模制构件（150）形成在封装衬底的上侧。 模制构件覆盖半导体芯片，导电连接构件和支撑构件。