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公开(公告)号：KR1020140037983A
公开(公告)日：2014-03-28
申请号：KR1020120099927
申请日：2012-09-10
Applicant: 삼성전자주식회사
IPC: H01L21/31 , H01L21/336 , H01L29/78
CPC classification number: H01L29/66666 , H01L21/76826 , H01L21/76828 , H01L21/76829 , H01L21/76837 , H01L29/495 , H01L29/4966 , H01L29/4975 , H01L29/517 , H01L29/66545 , H01L21/76832
Abstract: Provided is a method of manufacturing a semiconductor device which improves the density of a gap-fill insulating layer by using an expandable material. The method of manufacturing the semiconductor device includes forming a gate insulating layer on a substrate, forming a first and a second gate structure on the gate insulating layer, forming an expandable material on the first and the second gate structures, forming a gap-fill insulating layer between the expandable material and the first and the second gate structures, and performing a thermal process by increasing the volume of the expandable material.
Abstract translation: 提供一种通过使用可膨胀材料来提高间隙填充绝缘层的密度的半导体器件的制造方法。 制造半导体器件的方法包括在衬底上形成栅极绝缘层，在栅极绝缘层上形成第一和第二栅极结构，在第一和第二栅极结构上形成可膨胀材料，形成间隙填充绝缘 可膨胀材料与第一和第二栅极结构之间的层，并且通过增加可膨胀材料的体积来进行热处理。
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公开(公告)号：KR101921465B1
公开(公告)日：2018-11-26
申请号：KR1020120091811
申请日：2012-08-22
Applicant: 삼성전자주식회사
IPC: H01L29/78 , H01L21/336
CPC classification number: H01L27/088 , H01L21/764 , H01L27/0886 , H01L27/1116 , H01L27/1211
Abstract: 게이트와소오스및/또는드레인간의용량커플링(capacitive coupling) 현상을경감시킬수 있는반도체소자를제공하는것이다. 상기반도체소자는제1 영역및 제2 영역이정의되는기판, 상기제1 영역및 제2 영역상에각각형성된제1 트렌치및 제2 트렌치, 상기제1 트렌치및 상기제2 트렌치내에각각형성된제1 및제2 게이트패턴으로, 상기제1 및제2 게이트패턴은각각상기제1 및제2 트렌치를컨포말하게덮는제1 및제2 고유전율게이트절연막을포함하는제1 및제2 게이트패턴, 상기제1 게이트패턴의측벽상에형성되고, 제1 유전상수를갖는제1 절연층, 및상기제2 게이트패턴의측벽상에형성되고, 상기제1 유전상수와다른제2 유전상수를갖는제2 절연층을포함한다.
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公开(公告)号：KR1020140025746A
公开(公告)日：2014-03-05
申请号：KR1020120091811
申请日：2012-08-22
Applicant: 삼성전자주식회사
IPC: H01L29/78 , H01L21/336
CPC classification number: H01L27/088 , H01L21/764 , H01L27/0886 , H01L27/1116 , H01L27/1211 , H01L21/823468 , H01L29/4991
Abstract: Provided is a semiconductor device capable of reducing a capacitive coupling phenomenon among a gate, a source and/or a drain. The semiconductor device includes a substrate in which first and second areas are defined, first and second trenches formed on the first and second areas, respectively, first and second gate patterns formed in the first and second trenches, respectively, the first and second gate patterns including first and second high-permittivity gate insulating layers which conformally coat the first and second trenches, a first insulating layer formed on a side wall of the first gate pattern and having a first dielectric constant, and a second insulating layer formed on a side wall of the second gate pattern and having a second dielectric constant different from the first dielectric constant.
Abstract translation: 提供了能够减小栅极，源极和/或漏极之间的电容耦合现象的半导体器件。 半导体器件包括分别形成有第一和第二区域的衬底，分别形成在第一和第二区域上的第一和第二沟槽分别形成在第一和第二沟槽中的第一和第二栅极图案，第一和第二栅极图案 包括保形地涂覆第一和第二沟槽的第一和第二高电容率栅极绝缘层，形成在第一栅极图案的侧壁上并具有第一介电常数的第一绝缘层，以及形成在侧壁上的第二绝缘层 并具有与第一介电常数不同的第二介电常数。
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公开(公告)号：KR1020130007059A
公开(公告)日：2013-01-18
申请号：KR1020110063089
申请日：2011-06-28
Applicant: 삼성전자주식회사
IPC: H01L21/336 , H01L29/78
CPC classification number: H01L21/823456 , H01L21/82345 , H01L21/823842 , H01L21/82385 , H01L29/495 , H01L29/4966 , H01L29/4975 , H01L29/66545 , H01L29/66712
Abstract: PURPOSE: A method for manufacturing a semiconductor device is provided to implement a high speed operation at a low voltage by reducing the size of each pattern comprising a unit device. CONSTITUTION: An interlayer dielectric layer(114) is formed on a substrate(100). The interlayer dielectric layer includes a trench(115). A first metal layer, a second metal layer, and a third metal layer are formed on the interlayer dielectric layer. A sacrificial pattern is formed in the trench. A spacer pattern is formed on the side of the first metal layer.
Abstract translation: 目的：提供一种制造半导体器件的方法，通过减小包括单元器件的每个图案的尺寸来实现低电压的高速操作。 构成：在基板（100）上形成层间绝缘层（114）。 层间绝缘层包括沟槽（115）。 第一金属层，第二金属层和第三金属层形成在层间介电层上。 在沟槽中形成牺牲图案。 间隔图案形成在第一金属层的侧面上。
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公开(公告)号：KR1020080048767A
公开(公告)日：2008-06-03
申请号：KR1020060119141
申请日：2006-11-29
Applicant: 삼성전자주식회사
IPC: H01L21/76
Abstract: A method for forming an isolation structure is provided to suppress the generation of a void on a sidewall of a trench in an isolation pattern forming process for burying the trench. A first trench is formed on a substrate(100). A preliminary liner is formed on a bottom surface and a sidewall of the first trench. A liner(125) is obtained from the preliminary liner by annealing the resultant having the preliminary liner. A first preliminary oxide layer is formed on a surface of the liner. An overhang is removed and a first oxide layer having a second trench is formed when the first preliminary oxide has the overhang. A second oxide is formed to bury the second trench. A planarization process for the second oxide layer is performed to expose an upper surface of the substrate and to form a second oxide layer pattern.
Abstract translation: 提供一种用于形成隔离结构的方法，以在用于掩埋沟槽的隔离图案形成工艺中抑制在沟槽的侧壁上产生空隙。 在基板（100）上形成第一沟槽。 初步衬垫形成在第一沟槽的底表面和侧壁上。 通过对具有初步衬垫的所得物进行退火，从预衬里获得衬里（125）。 在衬垫的表面上形成第一预氧化物层。 当第一初步氧化物具有突出端时，移除突出端并形成具有第二沟槽的第一氧化物层。 形成第二氧化物以埋置第二沟槽。 执行第二氧化物层的平坦化处理以暴露衬底的上表面并形成第二氧化物层图案。
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Patent Agency Ranking
公开(公告)号：KR1020080048594A
公开(公告)日：2008-06-03
申请号：KR1020060118747
申请日：2006-11-29
Applicant: 삼성전자주식회사
IPC: H01L21/76
Abstract: A method for forming an isolation structure is provided to suppress the decrease of breakdown voltage by forming a re-oxidation layer for curing an exposed part of the damaged substrate. A trench(106) is formed on a substrate(100). A first oxide layer pattern(135) having a spacer structure is formed on a sidewall of the trench. A curing process is performed to cure an exposed surface of the substrate by using an oxidant while the first oxide layer pattern is formed on the sidewall of the trench. The trench is buried to form a second oxide layer pattern on the first oxide layer pattern and the exposed surface of the substrate. The oxidant includes oxygen, ozone, or nitric oxide. The curing process is performed by a radical oxidation process, a diffusion process, or a rapid thermal oxidation process.
Abstract translation: 提供一种用于形成隔离结构的方法，通过形成用于固化受损衬底的暴露部分的再氧化层来抑制击穿电压的降低。 在衬底（100）上形成沟槽（106）。 具有间隔结构的第一氧化物层图案（135）形成在沟槽的侧壁上。 进行固化处理，以通过使用氧化剂固化基板的暴露表面，同时在沟槽的侧壁上形成第一氧化物层图案。 掩埋沟槽以在第一氧化物层图案和基板的暴露表面上形成第二氧化物层图案。 氧化剂包括氧，臭氧或一氧化氮。 固化过程由自由基氧化法，扩散法或快速热氧化法进行。
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公开(公告)号：KR1020140110496A
公开(公告)日：2014-09-17
申请号：KR1020130024923
申请日：2013-03-08
Applicant: 삼성전자주식회사 , 서울대학교산학협력단
CPC classification number: A61M5/16831 , A61M5/14216 , A61M5/14244 , A61M5/14526 , A61M5/152 , A61M5/16854 , A61M5/16877 , A61M5/1723 , A61M5/5086 , A61M2205/332 , A61M2205/3523 , A61M2205/3569
Abstract: The present invention relates to a drug infusion pump comprising a main body including a driving motor and a processor; and a cartridge module detachable from the main body. As the cartridge module is installed to the main body, a pump module and a drug cartridge are accommodated in the main body, and the pump module is connected with the driving motor. The drug infusion pump can improve user convenience by being easily separated and replaced since the pump module connects to the driving motor by installing the cartridge module in the main body.
Abstract translation: 药液输注泵技术领域本发明涉及一种药液输注泵，其包括：主体，包括驱动电机和处理器; 以及可从主体拆卸的盒式模块。 当墨盒模块安装在主体上时，泵模块和药物盒容纳在主体中，并且泵模块与驱动马达连接。 由于泵模块通过将盒式模块安装在主体中而连接到驱动电机，因此药液输注泵可以通过容易地分离和更换而提高用户便利性。
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公开(公告)号：KR1020080025859A
公开(公告)日：2008-03-24
申请号：KR1020060090550
申请日：2006-09-19
Applicant: 삼성전자주식회사
IPC: H01L21/762
CPC classification number: H01L21/76224 , H01L21/0234
Abstract: A method for filling patterns of a semiconductor device is provided to form a trench having a positive lateral slope by partially removing an oxide layer at a side wall of the trench. By etching a surface of a semiconductor substrate(100) in a depth, a first trench(108) is formed. A first oxide layer having a first deposition speed is formed on the first trench and substrate. A second oxide layer having a second deposition speed quicker than the first deposition speed is formed on the first oxide layer. A part of the second and first oxide layers are removed at a lateral wall of the first trench, thereby forming a second trench(115) in the first trench. A third oxide layer(116) is formed to fill the second trench.
Abstract translation: 提供一种用于填充半导体器件的图案的方法，以通过在沟槽的侧壁部分去除氧化物层来形成具有正横向斜率的沟槽。 通过深度地蚀刻半导体衬底（100）的表面，形成第一沟槽（108）。 在第一沟槽和衬底上形成具有第一沉积速度的第一氧化物层。 在第一氧化物层上形成具有比第一沉积速度快的第二沉积速度的第二氧化物层。 在第一沟槽的侧壁处去除第二和第一氧化物层的一部分，从而在第一沟槽中形成第二沟槽（115）。 形成第三氧化物层（116）以填充第二沟槽。
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公开(公告)号：KR1020040103218A
公开(公告)日：2004-12-08
申请号：KR1020030035151
申请日：2003-05-31
Applicant: 삼성전자주식회사
IPC: H01L21/762
Abstract: PURPOSE: A method for forming a field oxide layer of a semiconductor device having an uniform surface is provided to perform easily a gap-fill process and form uniformly a surface of the field oxide layer by forming a spacer in an inner wall of a trench. CONSTITUTION: The first oxide layer is selectively formed on a peripheral region of a semiconductor substrate(200). A pad nitride layer is formed on the peripheral region and a cell region. A trench is formed by etching selectively the peripheral region and the cell region. The trench is buried by forming a primary oxide layer on the entire structure. The primary oxide layer is etched back. The second oxide layer is formed on the entire surface of the structure including the trench. A spacer is formed on a lateral part of the trench by etching the second oxide layer. The trench is buried by forming a secondary oxide layer on the structure including the spacer.
Abstract translation: 目的：提供一种形成具有均匀表面的半导体器件的场氧化物层的方法，以便容易地进行间隙填充处理，并且通过在沟槽的内壁中形成间隔物来均匀地形成场氧化物层的表面。 构成：第一氧化物层选择性地形成在半导体衬底（200）的外围区域上。 在周边区域和单元区域上形成衬垫氮化物层。 通过选择性地蚀刻外围区域和电池区域形成沟槽。 通过在整个结构上形成主氧化层来掩埋沟槽。 主氧化层被回蚀。 第二氧化物层形成在包括沟槽的结构的整个表面上。 通过蚀刻第二氧化物层，在沟槽的侧面部分上形成间隔物。 通过在包括间隔物的结构上形成二次氧化物层来掩埋沟槽。
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