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1.发明申请SDN에서 네트워크 장애 해소를 위한 컨트롤러 및 스위치의 동작 방법과, 이를 위한 컨트롤러 및 스위치 审中-公开用于操作控制器和开关的方法，用于从SDN中消除网络故障，以及控制器和开关
公开(公告)号：WO2015072709A1
公开(公告)日：2015-05-21
申请号：PCT/KR2014/010741
申请日：2014-11-10
Applicant: 삼성전자주식회사
IPC: H04L12/937 , H04L12/26
CPC classification number: H04L49/555 , H04L41/0654 , H04L43/10 , H04L45/22 , H04L45/28
Abstract: 본 발명의 실시예들은 SDN(Software-defined networking)에서 네트워크 장애 해소를 위한 컨트롤러 및 스위치의 동작 방법과, 이를 위한 컨트롤러 및 스위치를 제공한다. 본 발명의 일 실시예에 따르면, SDN에서 네트워크 장애 해소를 위한 컨트롤러의 동작방법은, 적어도 하나 이상의 스위치로부터 전송된 BFD(Bidirectional Forwarding Detection) 기능에 관한 BFD 수행능력정보를 포함하는 프로토콜 정보에 따라, 스위치들을 경유하는 데이터의 전송 경로에 관한 플로우 엔트리정보 및 상기 BFD 기능을 위해 상기 플로우 엔트리정보와 매핑된 세션 매핑정보를 생성하고, 상기 생성된 플로우 엔트리정보 및 상기 BFD 기능을 위한 설정을 지시하는 세션 설정신호를 상기 스위치로 전송하는 과정; 및 상기 스위치로부터 전송된 상기 BFD 기능에 의한 세션 상태에 따라, 상기 생성된 플로우 엔트리정보를 업데이트하는 과정을 포함한다.
Abstract translation: 本发明的实施例提供了一种用于操作控制器和用于从软件定义网络（SDN）以及控制器及其交换机中消除网络故障的开关的方法。 根据本发明的实施例，一种用于操作用于从SDN中消除网络故障的控制器的方法包括以下步骤：通过经由交换机的数据传输路径生成流入口信息，以及与流入口映射的会话映射信息 根据包括从至少一个交换机发送的BFD功能的BFD性能能力信息的协议信息，以及将生成的流入口信息和表示BFD功能的建立的会话建立信号发送到BFD功能的信息，用于双向转发检测（BFD）功能的信息， 开关; 根据从交换机发送的BFD功能，根据会话状态更新生成的流入口信息。
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公开(公告)号：KR1020170019745A
公开(公告)日：2017-02-22
申请号：KR1020150113972
申请日：2015-08-12
Applicant: 삼성전자주식회사
CPC classification number: A61B5/7285 , A61B5/0205 , A61B5/021 , A61B5/02438 , A61B5/0402 , A61B5/11 , A61B5/1118 , A61B5/14542 , A61B5/443 , A61B5/6801 , A61B5/681 , A61B5/6843 , A61B2560/0209 , A61B2562/0219 , A61B2562/0223 , A61B2562/0257 , G04G21/025 , G06F1/163 , G06F1/1684 , G06F1/1694 , G06F1/3215 , G06F1/3231 , G06F1/325 , Y02D10/173
Abstract: 본발명은배터리소모를줄이면서생체정보를검출하기위한장치에관한것으로, 하우징, 상기하우징의일부에결합되고, 사용자의신체의일부에착탈가능하게부착되는결착구, 상기전자장치의움직임을감지할수 있도록구성된적어도하나의제 1 센서, 상기사용자의신체의변화를감지할수 있도록구성된적어도하나의제 2 센서, 메모리및 상기제1 센서, 상기제2 센서, 및상기메모리와전기적으로연결된프로세서를포함할수 있다. 상기메모리는, 실행시에, 상기프로세서가, 상기적어도하나의제1 센서를이용하여상기전자장치가상기사용자의신체의일부에착용되었는지여부를판단하고, 상기전자장치가상기사용자의신체의일부에착용된시점으로부터선택된제1 시간주기 (a first period of time)를경과하는시점바로전(immediately before) 및/또는바로후(immediately after)의, 상기제1 시간주기보다짧은제2 시간주기동안에, 상기적어도하나의제1 센서의적어도일부를이용하여상기전자장치의움직임에관한정보를획득하고, 상기움직임에관한정보에적어도일부기초하여, 상기적어도하나의제2 센서를활성화(또는, 작동또는트리거)하도록하는인스트럭션들을저장할수 있다.
Abstract translation: 提供了一种用于检测生物特征信息的装置。 该装置包括壳体，联接到壳体的一部分并且可拆卸地附接到使用者身体的一部分的紧固件，配置成检测电子设备的运动的至少一个第一传感器，配置成检测 用户体内的变化，存储器和电连接到至少一个第一传感器，至少一个第二传感器和存储器的处理器。 存储器可以存储配置处理器的指令，当被执行时，使用至少一个第一传感器来确定电子设备是否佩戴在用户身体的一部分上，使用至少一个第一传感器获取关于电子设备的运动的信息 所述至少一个第一传感器的一部分在所选择的第一时间段之前不久和/或之后的第二时间段从所述电子设备佩戴在所述用户身体的一部分上的时间开始，并且至少激活所述至少一个 基于关于运动的信息的至少一部分的一秒传感器。
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公开(公告)号：KR1020140062601A
公开(公告)日：2014-05-26
申请号：KR1020120128224
申请日：2012-11-13
Applicant: 삼성전자주식회사
CPC classification number: H01L27/1052 , H01L21/76829 , H01L27/10876 , H01L27/10894 , H01L29/42336
Abstract: A semiconductor device and a method of manufacturing the same are provided. A semiconductor device may include a substrate having a cell region and a peripheral region, a cell gate electrode which is buried in a groove which crosses the cell active part of the cell region, a cell line pattern which crosses the upper part of the cell gate electrode and is connected to a first source/drain region which is formed in the cell active part of the one side of the cell gate electrode, a peripheral gate pattern which crosses the upper part of the peripheral active part of the peripheral region, a planarized interlayer dielectric which is arranged on the substrate around the peripheral gate pattern, and a capping insulating layer which is arranged on the planarized interlayer dielectric and the upper surface of the peripheral gate pattern. The capping insulating layer may include an insulating material which has etch selectivity to the planarized interlayer dielectric.
Abstract translation: 提供半导体器件及其制造方法。 半导体器件可以包括具有单元区域和外围区域的基板，埋在与单元区域的单元有源部分交叉的沟槽中的单元栅极电极，与单元栅极的上部交叉的单元线图案 并且连接到形成在单元栅电极的一侧的单元有源部分中的第一源极/漏极区域，与周边区域的外围有源部分的上部交叉的周边栅极图案，平面化 布置在周围栅极图案周围的基板上的层间电介质，以及布置在平坦化的层间电介质和外围栅极图案的上表面上的封盖绝缘层。 封盖绝缘层可以包括对平坦化的层间电介质具有蚀刻选择性的绝缘材料。
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Patent Agency Ranking
公开(公告)号：KR1020140052225A
公开(公告)日：2014-05-07
申请号：KR1020120117910
申请日：2012-10-23
Applicant: 삼성전자주식회사
IPC: H01L27/108 , H01L21/8242 , H01L21/28
CPC classification number: H01L27/0207 , H01L23/48 , H01L23/528 , H01L23/5329 , H01L27/10814 , H01L27/10855 , H01L27/10885 , H01L27/10888 , H01L2924/0002 , H01L2924/00
Abstract: A semiconductor device is provided. The semiconductor device includes a plurality of bit lines which intersect with an active region on a substrate and are extended in a first direction; a plurality of contact pads which are formed on the active region between the adjacent bit lines and include an epitaxial semiconductor layer; and a plurality of contact plugs which are formed on each contact pad between the adjacent bit lines.
Abstract translation: 提供半导体器件。 半导体器件包括与衬底上的有源区相交并且沿第一方向延伸的多个位线; 多个接触焊盘，形成在相邻位线之间的有源区上，并包括外延半导体层; 以及形成在相邻位线之间的每个接触焊盘上的多个接触插塞。
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公开(公告)号：KR1020140050212A
公开(公告)日：2014-04-29
申请号：KR1020120116178
申请日：2012-10-18
Applicant: 삼성전자주식회사
IPC: H01L27/108 , H01L21/8242
CPC classification number: H01L27/10888 , H01L21/26513 , H01L21/7682 , H01L21/76897 , H01L27/10855 , H01L27/10885
Abstract: The present invention relates to a semiconductor device and a manufacturing method thereof. According to one embodiment of the present invention, the semiconductor device and the manufacturing method thereof include a first impurity injection region and a second impurity injection region; a storage node contact which touches the first impurity injection region; a bit line; a bit line node contact which is arranged between the bit line and the impurity injection region; and a spacer. According to the present invention, a leakage current between the storage node contact and the bit line node contact can be prevented.
Abstract translation: 半导体器件及其制造方法技术领域本发明涉及半导体器件及其制造方法。 根据本发明的一个实施例，半导体器件及其制造方法包括第一杂质注入区和第二杂质注入区; 接触第一杂质注入区域的存储节点接点; 有点线 布置在位线和杂质注入区之间的位线节点接点; 和间隔物。 根据本发明，可以防止存储节点接点和位线节点接点之间的漏电流。
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公开(公告)号：KR1020140046526A
公开(公告)日：2014-04-21
申请号：KR1020120110128
申请日：2012-10-04
Applicant: 삼성전자주식회사
IPC: H01L29/78 , H01L21/336
CPC classification number: H01L27/10841 , H01L27/10864 , H01L27/10885 , H01L27/10891
Abstract: A semiconductor device according to an embodiment of the present invention includes: a semiconductor substrate, edge active pillars which protrude from the upper surface of the semiconductor substrate in a vertical direction, a center active pillar between the edge active pillars, a burying word lines which are arranged between the center active pillar and the edge active pillars, and a burying bit line which is arranged in the center active pillar and arranged in a diagonal direction to the burying word lines. The upper surface of the burying bit line is lower than the upper surface of the center active pillar. The lower surface of the burying bit line is higher than the upper surface of the burying word lines.
Abstract translation: 根据本发明的实施例的半导体器件包括：半导体衬底，沿着垂直方向从半导体衬底的上表面突出的边缘有源柱，在边缘有源柱之间的中心有源柱，埋入字线， 布置在中心主动支柱和边缘活动支柱之间，埋设位线布置在中心主动支柱中并沿对角线方向布置在掩埋字线上。 掩埋位线的上表面低于中心主动柱的上表面。 掩埋位线的下表面高于掩埋字线的上表面。
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公开(公告)号：KR1020140044445A
公开(公告)日：2014-04-15
申请号：KR1020120110400
申请日：2012-10-05
Applicant: 삼성전자주식회사
IPC: H01L21/8242 , H01L27/108
CPC classification number: H01L27/10855 , H01L21/76838 , H01L27/10823 , H01L27/10876 , H01L27/10885 , H01L27/10888
Abstract: The present invention relates to a method for manufacturing a semiconductor device comprising a step for etching the central part of active areas and forming a bit line contact area which is positioned less than the flat upper surface of a substrate; a step for forming a bit line structure on the bit line contact area; a step for forming a column silicon oxide film pattern which is touched to the upper surface of the edge part of the active area and the upper surface of a device separation film pattern; a step for filling both sides of the column silicon oxide film pattern and forming an interlayer insulating film by using an insulating material having the silicon oxide film pattern and an etching selective ratio; a step for forming a preparative contact hole by selectively removing the silicon oxide film pattern; a step for forming a contact hole which exposes the upper surface and a side of the edge part of the both sides of the active area by removing the device separation film pattern of the preparative contact hole; and a step for forming contact by filling a conductive material inside the contact hole. The present invention is provided to manufacture the semiconductor device comprising the contact having low resistance by increasing a contact area.
Abstract translation: 本发明涉及一种用于制造半导体器件的方法，包括用于蚀刻有源区的中心部分并形成位于小于衬底的平坦上表面的位线接触区域的步骤; 用于在位线接触区域上形成位线结构的步骤; 形成与活性区域的边缘部分的上表面和器件分离膜图案的上表面接触的柱状氧化硅膜图案的步骤; 通过使用具有氧化硅膜图案的绝缘材料和蚀刻选择比来填充柱状氧化硅膜图案的两侧并形成层间绝缘膜的步骤; 通过选择性地除去氧化硅膜图案形成制备接触孔的步骤; 形成接触孔的步骤，通过去除制备接触孔的器件分离膜图案来暴露有源区的两侧边缘部分的上表面和侧面; 以及通过在接触孔内填充导电材料来形成接触的步骤。 提供本发明以通过增加接触面积来制造包括具有低电阻的触点的半导体器件。
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公开(公告)号：KR1020130114983A
公开(公告)日：2013-10-21
申请号：KR1020120037481
申请日：2012-04-10
Applicant: 삼성전자주식회사
IPC: H01L27/10 , H01L21/8239 , H01L21/28
CPC classification number: H01L23/5384 , H01L21/76831 , H01L21/76877 , H01L21/76897 , H01L27/088 , H01L27/10876 , H01L27/10879 , H01L2924/0002 , H01L2924/00
Abstract: PURPOSE: A semiconductor device with a DC structure is provided to reduce contact resistance by including a top DC plug with a top part which is wider than a bottom part. CONSTITUTION: An interlayer dielectric layer is formed on a substrate. The substrate is exposed through a DC hole (160H). An insulating DC spacer is formed on the inner wall of the DC hole. A conductive DC plug is formed on the insulating DC spacer and includes a bottom DC plug (172) and a top DC plug (174). The top DC plug has a relatively wide horizontal width.
Abstract translation: 目的：提供具有直流结构的半导体器件，通过包括具有比底部部分更宽的顶部的顶部DC插头来降低接触电阻。 构成：在基板上形成层间绝缘层。 衬底通过DC孔（160H）暴露。 在DC孔的内壁上形成绝缘的DC间隔物。 导电直流插头形成在绝缘DC间隔件上，并包括底部直流插头（172）和顶部直流插头（174）。 顶部直流插头的水平宽度相对较宽。
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