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公开(公告)号：KR1020000066421A
公开(公告)日：2000-11-15
申请号：KR1019990013504
申请日：1999-04-16
Applicant: 삼성전자주식회사
IPC: H01L21/32
Abstract: PURPOSE: A method for manufacturing a semiconductor fine pattern is provided to stably etch the fine pattern when a polymer spacer is used as an etching mask, by hardening the polymer spacer using an ion injection. CONSTITUTION: A photoresist pattern(52) is formed on a specific layer. A part of the photoresist pattern is etched to form a polymer spacer(53) on a sidewall. An ion injection is performed regarding the photoresist pattern and polymer spacer. The specific layer is etched to form a fine pattern by using the photoresist pattern and polymer spacer as a mask.
Abstract translation: 目的：提供一种用于制造半导体精细图案的方法，通过使用离子注入对聚合物间隔物进行硬化，以使用聚合物间隔物作为蚀刻掩模来稳定蚀刻精细图案。 构成：在特定层上形成光致抗蚀剂图案（52）。 蚀刻光致抗蚀剂图案的一部分以在侧壁上形成聚合物间隔物（53）。 对光致抗蚀剂图案和聚合物间隔物进行离子注入。 通过使用光致抗蚀剂图案和聚合物间隔物作为掩模来蚀刻特定层以形成精细图案。
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公开(公告)号：KR1020000061200A
公开(公告)日：2000-10-16
申请号：KR1019990010082
申请日：1999-03-24
Applicant: 삼성전자주식회사
Inventor： 백재학
IPC: H01L27/085
Abstract: PURPOSE: A capacitor of a semiconductor device and a fabrication method thereof are provided to improve capacitance without increasing the height of a storage electrode of the capacitor. CONSTITUTION: A capacitor includes a semiconductor substrate(21) on which field isolation layers(23) and gate electrodes(25) are selectively formed, and an interlayered dielectric layer(27) having buried contact holes(29) through which the semiconductor substrate(21) is exposed. The contact holes(29) are filled with a first polysilicon layer pattern(33) to be used as a storage electrode. In addition, a U-shaped second polysilicon layer pattern(43) is formed on both the dielectric layer(27) and the first polysilicon layer pattern(33). As a result, the storage electrode of the capacitor is composed of a first and a second polysilicon layer patterns(33,43). Accordingly, the height of the storage electrode keeps unchanged, however the capacitance of the capacitor is increased.
Abstract translation: 目的：提供半导体器件的电容器及其制造方法，以提高电容而不增加电容器的存储电极的高度。 构成：电容器包括其上选择性地形成有场隔离层（23）和栅电极（25）的半导体衬底（21），以及具有掩埋接触孔（29）的层间介电层（27），半导体衬底 21）暴露。 接触孔（29）填充有用作存储电极的第一多晶硅层图案（33）。 此外，在电介质层（27）和第一多晶硅层图案（33）两者之间形成U形的第二多晶硅层图案（43）。 结果，电容器的存储电极由第一和第二多晶硅层图案（33,43）组成。 因此，存储电极的高度保持不变，然而电容器的电容增加。
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公开(公告)号：KR1020000013325A
公开(公告)日：2000-03-06
申请号：KR1019980032135
申请日：1998-08-07
Applicant: 삼성전자주식회사
Inventor： 백재학
IPC: H01L21/304
Abstract: PURPOSE: A chamber equipment using at fabricating process of semiconductor device and method for processing wafer using thereof is provided to completely remove a residue of reaction on a wafer. CONSTITUTION: The chamber equipment has a reaction chamber and a load lock chamber. A ceiling of the load lock chamber is constituted transparent material. A reflecting shade is installed both side ends of the ceiling. A heater is installed between the reflecting shade and the ceiling to heat internal of the load lock chamber. A surface facing the load lock chamber of the reflecting shade is constituted a reflecting surface to improve efficiency of a heating.
Abstract translation: 目的：提供一种在制造半导体器件的过程中使用的室内设备及其使用晶片处理方法，以完全去除晶片上的反应残留物。 构成：腔室设备具有反应室和负载锁定室。 负载锁定室的天花板构成透明材料。 反光罩安装在天花板的两侧。 加热器安装在反光罩和天花板之间，以加热负载锁定室的内部。 面对反射罩的负载锁定室的表面构成为提高加热效率的反射面。
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Patent Agency Ranking
公开(公告)号：KR100252042B1
公开(公告)日：2000-05-01
申请号：KR1019970057753
申请日：1997-11-03
Applicant: 삼성전자주식회사
IPC: H01L21/28
CPC classification number: H01L21/76838 , H01L21/32137
Abstract: PURPOSE: A method for manufacturing semiconductor device having wiring made of a doped polysilicon film is provided to prevent portion of a doped polysilicon film from being scattered by supplying gases containing carbon and oxygen in blanket etching of the doped polysilicon film. CONSTITUTION: An etched-back polysilicon film(29a) having smaller thickness than that of a doped polysilicon film is formed by a blanket etching process of the doped polysilicon film. At this time, the doped polysilicon film is etched by performing a reactive ion etching process or a magnetic enhancement reactive ion etching process. During this etching process, gases containing carbon and oxygen in addition to gases containing SF6 and chlorine are additionally supplied. These carbon atoms increase binding force between silicon grains.
Abstract translation: 目的：提供一种制造具有由掺杂多晶硅膜制成的布线的半导体器件的方法，以通过在掺杂多晶硅膜的覆盖蚀刻中提供含有碳和氧的气体来防止掺杂多晶硅膜的部分散射。 构成：通过掺杂多晶硅膜的覆盖蚀刻工艺形成具有比掺杂多晶硅膜厚度小的蚀刻回蚀多晶硅膜（29a）。 此时，通过执行反应离子蚀刻工艺或磁性增强反应离子蚀刻工艺来蚀刻掺杂多晶硅膜。 在该蚀刻过程中，除了含有SF6和氯的气体之外，还附加了含有碳和氧的气体。 这些碳原子增加了硅晶粒之间的结合力。
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公开(公告)号：KR1019990038118A
公开(公告)日：1999-06-05
申请号：KR1019970057753
申请日：1997-11-03
Applicant: 삼성전자주식회사
IPC: H01L21/28
Abstract: 본 발명은 도우프트 폴리실리콘막으로 구성되는 배선을 갖는 반도체소자의 제조방법을 개시한다. 반도체기판 상에 콘택홀을 갖는 층간절연막 패턴을 형성하고, 층간절연막 패턴 전면에 콘택홀을 채우는 두꺼운 도우프트 폴리실리콘막을 형성한다. 도우프트 폴리실리콘막을 탄소를 포함하는 가스 및 산소를 포함하는 가스를 사용하여 전면식각함으로써, 층간절연막 패턴 상에 균일한 두께를 갖고 표면에 탄소원자층이 제거된 에치백된 폴리실리콘막을 형성한다. 에치백된 폴리실리콘막 상에 금속 실리사이드막을 형성한 다음, 금속 실리사이드막 및 에치백된 폴리실리콘막을 연속적으로 패터닝하여 배선을 형성한다.
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公开(公告)号：KR1020000061306A
公开(公告)日：2000-10-16
申请号：KR1019990010256
申请日：1999-03-25
Applicant: 삼성전자주식회사
IPC: H01L21/28
Abstract: PURPOSE: A method for manufacturing a metal fuse of a semiconductor device is provided to decrease or minimize a defect of a metal fuse by completely eliminating a horn-type passivation oxidation layer. CONSTITUTION: A method for manufacturing a metal fuse of a semiconductor device comprises the steps of: forming a passivation layer(40) covering a metal layer formed on a barrier metal layer(20) to be used for a fuse, and forming a photoresist pattern exposing a part of the passivation layer; anisotropically etching a predetermined thickness of the passivation layer by using the photoresist pattern as an etch mask, and etching the exposed metal layer by a predetermined thickness; and anisotropically etching a predetermined thickness of the passivation layer again by using the etch mask, and repeatedly etching the exposed metal layer by a predetermined thickness, so that the metal layer and the passivation layer are completely etched and the barrier metal layer remains as the fuse.
Abstract translation: 目的：提供一种用于制造半导体器件的金属熔丝的方法，以通过完全消除喇叭型钝化氧化层来减少或最小化金属熔丝的缺陷。 构成：用于制造半导体器件的金属熔丝的方法包括以下步骤：形成覆盖形成在用于保险丝的阻挡金属层（20）上的金属层的钝化层（40），并形成光致抗蚀剂图案 暴露一部分钝化层; 通过使用光致抗蚀剂图案作为蚀刻掩模，各向异性蚀刻钝化层的预定厚度，并将暴露的金属层蚀刻预定厚度; 并通过使用蚀刻掩模再次蚀刻预定厚度的钝化层，并且将暴露的金属层重复蚀刻预定厚度，使得金属层和钝化层被完全蚀刻，并且阻挡金属层保持为保险丝 。
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公开(公告)号：KR1019990032973A
公开(公告)日：1999-05-15
申请号：KR1019970054198
申请日：1997-10-22
Applicant: 삼성전자주식회사
IPC: H01L21/68
Abstract: 본 발명은 반도체장치의 제조설비 및 이 설비에 대한 웨이퍼 출입방법에 관해 개시한다. 본 발명은 반도체장치에 제조설비중 챔버 예컨데 로드 락 챔버에 압력 완충 수단을 구비한다. 상기 압력 완충 수단은 밸브나 필터 또는 이들의 조합으로 구성할 수 있다. 상기 압력 완충 수단에 의해 상기 로드 락 챔버의 내, 외부가 열역학적으로 평형상태가 될 수 있다. 따라서, 웨이퍼 카세트로부터 상기 로드 락 챔버로 웨이퍼가 출입되거나 그 반대의 경우, 두 영역간의 압력차에 의해 발생되는 와류를 방지할 수 있으므로 상기 와류에 기인한 웨이퍼의 파티클 오염을 방지할 수 있다.
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公开(公告)号：KR1019980021218A
公开(公告)日：1998-06-25
申请号：KR1019960040005
申请日：1996-09-14
Applicant: 삼성전자주식회사
IPC: H01L21/3065
Abstract: 반도체 소자의 건식 식각 방법이 개시되어 있다. 본 발명에 따른 건식 식각 방법에서는 반도체 소자에 사용되는 도전층 패턴을 형성하기 위하여 패시베이션 가스로서 O
2 /Cl
2 가스를 공급한다. 본 발명에 의하면, 환경 오염에 따른 문제를 방지할 수 있고, 웨이퍼당 공정 진행 시간이 단축될 수 있으며, 애싱 및 스트립 공정시 비교적 짧은 시간이 소요된다.
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