公开(公告)号：KR1020140055120A

公开(公告)日：2014-05-09

申请号：KR1020120121492

申请日：2012-10-30

Applicant: 삼성전자주식회사

Inventor： 안용훈 ,  배용철 ,  정용권 ,  최종현

IPC: G11C7/10

CPC classification number: G11C7/1048 ,  G11C2207/105 ,  G11C2207/2254 ,  H03K19/0005

Abstract: Disclosed is a semiconductor memory device including an on-die termination circuit which is enabled or disabled in response to a clock enable signal. The on-die termination circuit includes a termination resistor which is enabled or disabled in response to a clock enable signal. Accordingly, the semiconductor memory device has a low power consumption.

Abstract translation: 公开了一种包括片上终端电路的半导体存储器件，该片上终端电路响应于时钟使能信号被使能或禁止。 片上终端电路包括响应于时钟使能信号使能或禁止的终端电阻。 因此，半导体存储器件具有低功耗。

公开(公告)号：KR1020080007808A

公开(公告)日：2008-01-23

申请号：KR1020060066933

申请日：2006-07-18

Applicant: 삼성전자주식회사

Inventor： 정용권

IPC: G11C7/20 ,  G11C7/10

CPC classification number: G11C7/1051 ,  G11C7/1057 ,  G11C7/20

Abstract: A semiconductor device comprising a reset circuit for an output buffer and a method for resetting the output buffer are provided to prevent power-up or power-down of one memory chip in a multi-chip package from influencing on data outputted from the other memory chip. A semiconductor device comprises at least two semiconductor memory devices. Each semiconductor memory device comprises a memory cell array having memory cells arranged in a matrix of rows and columns, a peripheral circuit and an output buffer. The peripheral circuit writes data into a cell of the memory cell array, and reads and amplifies written data. The output buffer outputs cell data amplified in the peripheral circuit. The output buffer comprises an output buffer reset circuit(110) and an output driver. The output buffer reset circuit enables an output buffer reset signal in response to power-up or power-down of the semiconductor memory device, and disables the output buffer reset signal in response to a first command signal received from a controller of the semiconductor memory device. The output driver generates output data on the basis of a data signal, in response to a clock signal, a data enable signal and the output buffer reset signal.

Abstract translation: 提供了包括用于输出缓冲器的复位电路和用于复位输出缓冲器的方法的半导体器件，以防止多芯片封装中的一个存储器芯片的上电或掉电，从而影响从另一个存储器芯片输出的数据 。 半导体器件包括至少两个半导体存储器件。 每个半导体存储器件包括具有以行和列的矩阵排列的存储单元的存储单元阵列，外围电路和输出缓冲器。 外围电路将数据写入存储单元阵列的单元，并读取并放大写入的数据。 输出缓冲器输出外围电路放大的单元数据。 输出缓冲器包括输出缓冲器复位电路（110）和输出驱动器。 输出缓冲器复位电路响应于半导体存储器件的上电或掉电而启用输出缓冲器复位信号，并且响应于从半导体存储器件的控制器接收的第一命令信号而禁用输出缓冲器复位信号 。 输出驱动器响应于时钟信号，数据使能信号和输出缓冲器复位信号，基于数据信号产生输出数据。

公开(公告)号：KR1020100104686A

公开(公告)日：2010-09-29

申请号：KR1020090023265

申请日：2009-03-18

Applicant: 삼성전자주식회사

Inventor： 손영훈 ,  박광일 ,  정용권 ,  김시홍

IPC: G01R27/02

CPC classification number: H04L25/0278

Abstract: PURPOSE: A semiconductor device for the test of the impedance calibration code transmission line is provided to test a code transmission path by serially outputting a test code through an OCD(Off Chip Driver) and an ODT(On-Die Termination). CONSTITUTION: An impedance calibration part(20) is connected to a pad which is connected to an external reference resistor. An impedance calibration code having the impedance correspondence value of a reference resistor is generated and is outputted to a code transmission line. A test code is outputted to the code transmission line according to the test signal when the test is executed. An impedance matching part executes an impedance matching operation in response to the impedance calibration code during a normal operation process.

Abstract translation: 目的：提供一种用于测试阻抗校准码传输线的半导体器件，用于通过OCD（片外驱动器）和ODT（片内终端）串行输出测试代码来测试代码传输路径。 构成：阻抗校准部件（20）连接到连接到外部参考电阻器的焊盘。 产生具有参考电阻的阻抗对应值的阻抗校准码，并将其输出到码传输线。 当执行测试时，根据测试信号将测试代码输出到代码传输线。 阻抗匹配部件在正常操作过程中响应于阻抗校准码执行阻抗匹配操作。

公开(公告)号：KR101292687B1

公开(公告)日：2013-08-02

申请号：KR1020060066933

申请日：2006-07-18

Applicant: 삼성전자주식회사

Inventor： 정용권

IPC: G11C7/20 ,  G11C7/10

CPC classification number: G11C7/1051 ,  G11C7/1057 ,  G11C7/20

Abstract: 출력 버퍼 초기화 회로를 구비하는 반도체 장치 및 출력 버퍼 초기화 방법이 개시된다. 상기 본 발명의 반도체 장치는, 적어도 두 개의 반도체 메모리 장치들을 구비하며 상기 반도체 메모리 장치들 각각은 메모리 셀 어레이, 주변회로, 및 출력 버퍼를 구비하며, 상기 출력 버퍼는 상기 반도체 메모리 장치에 리드 명령 신호가 입력되기 전에 입력되는 소정의 명령 신호에 기초하여 상기 출력 버퍼의 출력단자를 고 저항상태를 유지함으로써 상기 반도체 메모리 장치가 파워 업(power up)될 때 다른 반도체 메모리 장치에서 출력되는 데이터에 영향을 주지않는 효과가 있다.
멀티 칩 패키지, 출력 버퍼

公开(公告)号：KR1020100013167A

公开(公告)日：2010-02-09

申请号：KR1020080074715

申请日：2008-07-30

Applicant: 삼성전자주식회사

Inventor： 정용권 ,  박광일 ,  안민수

IPC: G11C7/10 ,  G11C7/22

CPC classification number: G11C7/1051 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/222 ,  G11C2207/2254 ,  H03K5/133 ,  H03K2005/00078

Abstract: PURPOSE: A semiconductor device is provided to uniformly maintain a data accessing time by delaying a clock signal for a predetermined time. CONSTITUTION: A controller generates a control signal in response to the output signal of a calibration circuit(110). A delay unit(150) delays a clock signal in response to the control signal. A delay unit outputs the clock signal to an output driver. A control unit(130) generates the control signal using a relation between the signal transmission speed of a semiconductor device and the output signal of a calibration circuit. The calibration circuit is a ZQ calibration circuit.

Abstract translation: 目的：提供一种半导体器件，用于通过在预定时间内延迟时钟信号来均匀地维持数据访问时间。 构成：控制器响应于校准电路（110）的输出信号产生控制信号。 延迟单元（150）响应于控制信号延迟时钟信号。 延迟单元将时钟信号输出到输出驱动器。 控制单元（130）使用半导体器件的信号传输速度与校准电路的输出信号之间的关系来生成控制信号。 校准电路是一个ZQ校准电路。

公开(公告)号：KR1020090100540A

公开(公告)日：2009-09-24

申请号：KR1020080025785

申请日：2008-03-20

Applicant: 삼성전자주식회사

Inventor： 김미조 ,  유학수 ,  손한구 ,  정용권 ,  원명규

IPC: G11C11/4093 ,  G11C11/4096 ,  G11C11/4076

CPC classification number: G11C11/4093 ,  G11C7/1006 ,  G11C7/1051 ,  G11C11/40611 ,  G11C11/4076 ,  G11C11/4096 ,  G11C2207/2272

Abstract: PURPOSE: A semiconductor memory device is provided to fetch the data using a data strobe signal in an operation with a high frequency. CONSTITUTION: A memory cell array stores the data in a writing operation. The memory cell array outputs the data in a reading operation. A mode setting unit sets a read latency and a burst length in response to a code signal applied from the outside in a mode setting operation. A clock frequency sensor(18) outputs a preamble cycle signal by counting the number of external clocks applied from the outside for a period corresponding the delay time of a data output path output the data of the memory cell array to the outside. A latency signal generator is activated prior to the period corresponding to the preamble cycle signal before outputting the data stored in the memory cell array to the outside in a read latency period. The latency signal generator generates the data strobe latency signal which is inactivated after maintaining an activation period as many as the period adding the burst length in the period corresponding to the preamble cycle signal.

Abstract translation: 目的：提供一种半导体存储器件，用于在高频操作中使用数据选通信号来取出数据。 构成：存储单元阵列将数据存储在写入操作中。 存储单元阵列在读取操作中输出数据。 模式设置单元响应于在模式设置操作中从外部施加的代码信号设置读延迟和突发长度。 时钟频率传感器（18）通过对从输出存储单元阵列的数据到外部的数据输出路径的延迟时间相对应的周期对来自外部的外部时钟数进行计数来输出前同步码周期信号。 在等待时间周期内将存储在存储单元阵列中的数据输出到外部之前，等待时间信号发生器在对应于前导码周期信号的周期之前被激活。 等待时间信号发生器产生数据选通等待时间信号，该信号在维持与在前同步码周期信号相对应的周期中添加脉冲串长度的周期的激活周期之后被激活。