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公开(公告)号：KR1020080026859A
公开(公告)日：2008-03-26
申请号：KR1020060091960
申请日：2006-09-21
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L27/115
CPC classification number: H01L27/11521 , H01L21/28141 , H01L21/28273 , H01L21/31051 , H01L21/76897
Abstract: A method for manufacturing a non-volatile memory device is provided to uniformly form a tunneling insulating layer by evenly forming a side profile of a floating gate. An insulating layer and a conducting layer for a floating gate are deposited on a semiconductor substrate(100), and then are patterned to form a gate insulating layer(210) and a floating gate(220). A spacer(310) is formed on one side of the floating gate, and the substrate is subjected to an oxidation process to form an integrated insulating layer(230), and then the spacer is removed. The substrate is subjected to an oxidation process to form a tunneling insulating layer on the substrate and at one side of the floating gate. A control gate is formed on the floating gate, a source region is formed at one side of the floating gate, and then a drain region is formed at one side of the control gate.
Abstract translation: 提供一种用于制造非易失性存储器件的方法，通过均匀地形成浮动栅极的侧面轮廓来均匀地形成隧道绝缘层。 绝缘层和用于浮置栅极的导电层沉积在半导体衬底（100）上，然后被图案化以形成栅绝缘层（210）和浮栅（220）。 在浮置栅极的一侧上形成间隔物（310），并对衬底进行氧化处理以形成一体的绝缘层（230），然后移除间隔物。 对衬底进行氧化处理，以在衬底上和浮栅的一侧形成隧道绝缘层。 在浮置栅极上形成控制栅极，在浮置栅极的一侧形成源极区域，然后在控制栅极的一侧形成漏极区域。
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公开(公告)号：KR101287447B1
公开(公告)日：2013-07-19
申请号：KR1020070086678
申请日：2007-08-28
Applicant: 삼성전자주식회사
IPC: G11C16/26 , G11C16/30 , H01L27/115
CPC classification number: G11C16/0433 , G11C16/26 , H01L27/105 , H01L27/11526 , H01L27/11529
Abstract: 이이피롬 셀, 이이피롬 셀 제조 방법 및 이이피롬 셀에서의 데이터 읽기 방법에서, 메모리 트랜지스터 및 선택 트랜지스터를 포함하는 이이피롬 셀의 읽기 방법으로, 상기 이이피롬 셀의 비트 라인에 읽기용 비트 라인 전압을 인가한다. 상기 셀에 포함된 메모리 트랜지스터의 센스 라인에 제1 전압을 인가한다. 상기 셀에 포함된 선택 트랜지스터의 워드 라인에 상기 제1 전압보다 높은 제2 전압을 인가한다. 다음에, 상기 셀을 통해 흐르는 전류를 기준 전류와 비교함으로써 상기 셀에 저장된 데이터를 판별한다. 상기 읽기 방법에 의하면, 상기 셀이 소거 상태일 때 셀의 온 전류가 증가하게 되어 데이터 판별이 용이하다.
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公开(公告)号：KR1020090021830A
公开(公告)日：2009-03-04
申请号：KR1020070086678
申请日：2007-08-28
Applicant: 삼성전자주식회사
IPC: G11C16/26 , G11C16/30 , H01L27/115
CPC classification number: G11C16/0433 , G11C16/26 , H01L27/105 , H01L27/11526 , H01L27/11529 , H01L21/28273
Abstract: An EEPROM cell, a manufacturing method thereof, a method for reading data in the same are provided to increase an on cell current of a memory cell by supplying a high voltage to a word line. A memory transistor(102) includes a first gate structure and a source/drain region. The first gate structure has a tunnel oxide film, a floating gate electrode, a dielectric film pattern, and a control gate electrode. A selection transistor(104) is connected to the memory transistor, and includes a second gate structure and a source/drain region. The second gate structure has a gate oxide film pattern and a gate electrode. An output terminal of a charge pumping circuit(110) is connected to the gate electrode of the second gate structure in order to supply a boosted voltage to the gate electrode of the selection transistor. A resistance line(140) connects the output terminal of the charge pumping circuit to the control gate electrode, and includes a resistor.
Abstract translation: 提供EEPROM单元及其制造方法，用于读取数据的方法，以通过向字线提供高电压来增加存储单元的导通单元电流。 存储晶体管（102）包括第一栅极结构和源极/漏极区域。 第一栅极结构具有隧道氧化膜，浮栅电极，电介质膜图案和控制栅电极。 选择晶体管（104）连接到存储晶体管，并且包括第二栅极结构和源极/漏极区域。 第二栅极结构具有栅极氧化膜图案和栅电极。 电荷泵浦电路（110）的输出端子连接到第二栅极结构的栅电极，以便向选择晶体管的栅电极提供升压电压。 电阻线（140）将电荷泵送电路的输出端子连接到控制栅电极，并且包括电阻器。
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