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公开(公告)号：WO2018139749A1
公开(公告)日：2018-08-02
申请号：PCT/KR2017/013323
申请日：2017-11-22
Applicant: 삼성전자주식회사
CPC classification number: C23C28/04 , C25D11/04 , C25D11/16 , C25D11/18 , C25D11/24 , C25D11/26 , C25D11/30 , H04M1/02
Abstract: 다양한 실시예에 따르면, 금속 재질의 금속 모재를 형성하는 공정과, 상기 금속 모재의 표면에 일정 광택도 및 평탄도를 갖도록 전처리하는 공정과, 상기 금속 모재의 평탄면에 일정한 산화피막을 형성시키는 아노다이징 공정과, 소망 컬러를 갖는 착색제를 이용하여 상기 산화피막을 착색 처리하는 공정과, 상기 착색 처리된 산화 피막의 착색제의 성능 및 특성 유지를 위한 봉공 공정 및 상기 봉공 처리된 산화피막의 상부에 적어도 하나의 증착층을 적층시키는 공정을 포함하는 금속 하우징 제조 방법을 제공할 수 있다.
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公开(公告)号：KR1020090039610A
公开(公告)日：2009-04-22
申请号：KR1020080097406
申请日：2008-10-02
Applicant: 삼성전자주식회사 , 재단법인서울대학교산학협력재단
IPC: H01L27/115 , H01L21/8247 , B82Y10/00
CPC classification number: H01L21/28282 , B82Y10/00 , H01L27/11568 , H01L29/4234 , H01L29/66833 , H01L29/792
Abstract: A semiconductor device and an operation method thereof are provided to apply different nanostructures to one element and to arrange the predetermined nano structure on a required region of a substrate accurately. A channel layer(C1) includes a first nanostructure(n1). A source and a drain are contacted with both ends of the channel layer. A first tunnel insulating layer(TL1) is equipped on the channel layer. A first charge trapping layer(CT1) is equipped on the first tunnel insulating layer. The first charge trapping layer includes a first nano structure and a second nano structure(n2). A first blocking insulating layer(BL1) is equipped on the first charge trapping layer. A first control gate is equipped on the first block insulating layer.
Abstract translation: 提供半导体器件及其操作方法以将不同的纳米结构应用于一个元件并且将预定的纳米结构精确地布置在基板的所需区域上。 沟道层（C1）包括第一纳米结构（n1）。 源极和漏极与沟道层的两端接触。 沟道层上装有第一隧道绝缘层（TL1）。 在第一隧道绝缘层上装有第一电荷俘获层（CT1）。 第一电荷俘获层包括第一纳米结构和第二纳米结构（n2）。 在第一电荷俘获层上装有第一阻挡绝缘层（BL1）。 第一控制门装在第一块绝缘层上。
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公开(公告)号：KR1020080026859A
公开(公告)日：2008-03-26
申请号：KR1020060091960
申请日：2006-09-21
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L27/115
CPC classification number: H01L27/11521 , H01L21/28141 , H01L21/28273 , H01L21/31051 , H01L21/76897
Abstract: A method for manufacturing a non-volatile memory device is provided to uniformly form a tunneling insulating layer by evenly forming a side profile of a floating gate. An insulating layer and a conducting layer for a floating gate are deposited on a semiconductor substrate(100), and then are patterned to form a gate insulating layer(210) and a floating gate(220). A spacer(310) is formed on one side of the floating gate, and the substrate is subjected to an oxidation process to form an integrated insulating layer(230), and then the spacer is removed. The substrate is subjected to an oxidation process to form a tunneling insulating layer on the substrate and at one side of the floating gate. A control gate is formed on the floating gate, a source region is formed at one side of the floating gate, and then a drain region is formed at one side of the control gate.
Abstract translation: 提供一种用于制造非易失性存储器件的方法，通过均匀地形成浮动栅极的侧面轮廓来均匀地形成隧道绝缘层。 绝缘层和用于浮置栅极的导电层沉积在半导体衬底（100）上，然后被图案化以形成栅绝缘层（210）和浮栅（220）。 在浮置栅极的一侧上形成间隔物（310），并对衬底进行氧化处理以形成一体的绝缘层（230），然后移除间隔物。 对衬底进行氧化处理，以在衬底上和浮栅的一侧形成隧道绝缘层。 在浮置栅极上形成控制栅极，在浮置栅极的一侧形成源极区域，然后在控制栅极的一侧形成漏极区域。
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公开(公告)号：KR1020030021905A
公开(公告)日：2003-03-15
申请号：KR1020010055467
申请日：2001-09-10
Applicant: 삼성전자주식회사
CPC classification number: H01L29/66772 , H01L29/78624
Abstract: PURPOSE: A semiconductor device on a silicon-on-insulator(SOI) is provided to guarantee a sufficient ground region by forming an asymmetrical source/drain junction with respect to a gate. CONSTITUTION: A semiconductor substrate has a SOI structure in which an insulation layer(100b) of a predetermined thickness is formed and a single crystal silicon layer(100c) is formed on the insulation layer. An isolation layer(110) is formed on the insulation layer on the semiconductor substrate. A gate includes the single crystal silicon layer formed between the isolation layers, a gate insulation layer(121) and a gate conductive layer(122). An insulation layer spacer(130) is formed on the sidewall of the gate. A source junction(150) and a drain junction(160) are asymmetrically formed at both sides of the gate in a region between the gate spacer and the isolation layer.
Abstract translation: 目的：提供绝缘体上硅（SOI）上的半导体器件，以通过相对于栅极形成不对称的源极/漏极结来保证足够的接地区域。 构成：半导体衬底具有其中形成预定厚度的绝缘层（100b）并且在绝缘层上形成单晶硅层（100c）的SOI结构。 隔离层（110）形成在半导体衬底上的绝缘层上。 栅极包括形成在隔离层之间的单晶硅层，栅极绝缘层（121）和栅极导电层（122）。 绝缘层隔离物（130）形成在栅极的侧壁上。 源极结（150）和漏极结（160）在栅极间隔物和隔离层之间的区域中不对称地形成在栅极的两侧。
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公开(公告)号：KR1020000001886A
公开(公告)日：2000-01-15
申请号：KR1019980022362
申请日：1998-06-15
Applicant: 삼성전자주식회사
Inventor： 임지운
IPC: H01L21/302
Abstract: PURPOSE: A semiconductor device production method is provided to reduce step difference between a logic circuit part and a memory cell array part. CONSTITUTION: The semiconductor element production method comprises steps of; forming a flattening layer between a logic circuit part and a memory element part on the substrate; forming a 1st metal film on the flattening layer; forming a 1st interlayer insulation film on overall the resultant topography of the area where a metal film is formed; forming a 1st plug conductive layer to fill up a bare hole.
Abstract translation: 目的：提供一种半导体器件制造方法，用于减少逻辑电路部分和存储单元阵列部分之间的阶差。 构成：半导体元件制造方法包括以下步骤： 在所述基板上的逻辑电路部和存储元件部之间形成平坦化层; 在平坦层上形成第一金属膜; 在形成金属膜的区域的总体形成第一层间绝缘膜; 形成第一插头导电层以填充裸露的孔。
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Patent Agency Ranking
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公开(公告)号：KR1020060085873A
公开(公告)日：2006-07-28
申请号：KR1020050006834
申请日：2005-01-25
Applicant: 삼성전자주식회사
Inventor： 임지운
IPC: H01L27/115
CPC classification number: H01L27/11521 , H01L27/115 , H01L29/0692 , H01L29/42324 , H01L29/7881 , H01L21/28273
Abstract: 프로그램 및 소거 효율을 증대시킬 수 있는 비휘발성 메모리 소자 및 그 형성 방법을 개시한다. 이 소자는, 반도체 기판에 위치하여 활성 영역을 정의하는 복수개의 소자 분리막들; 상기 소자분리막들 상을 가로지르되, 서로 평행한 복수개의 워드라인들; 상기 활성 영역에서 상기 반도체 기판과 상기 워드라인 사이에 적어도 일부 개재되는 부유 게이트; 상기 부유 게이트와 상기 활성 영역 사이에 개재되는 터널 산화막; 상기 부유 게이트와 상기 워드라인 사이에 개재되는 게이트 층간절연막; 상기 워드라인의 일 측의 상기 활성 영역에 위치하는 소오스 영역; 및 상기 워드라인의 다른 측의 상기 활성 영역에 위치하는 드레인 영역을 구비한다. 상기 부유 게이트는, 상기 소오스 영역과 접하는 제 1 변, 및 상기 소오스 영역과 접하지 않으나 상기 워드라인과 접하는 제 2 변을 구비하며, 적어도 상기 제 1 변은 굴곡진 것을 특징으로 한다.
스플리트 게이트형 비휘발성 메모리 소자. 부유 게이트-
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公开(公告)号：KR1020140024609A
公开(公告)日：2014-03-03
申请号：KR1020120090784
申请日：2012-08-20
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L23/48 , H01L27/11575 , H01L27/11582 , H01L2924/0002 , H01L27/0688 , H01L2924/00
Abstract: A 3D nonvolatile memory device and a fabricating method thereof are provided. The 3D nonvolatile memory device includes a substrate where a cell array region and a connection region are defined, an electrode structure which is formed on the cell array region and the connection region and includes stacked electrodes, a second recess formed on the electrode structure on the connection region, a first recess which is formed on the electrode structure of the connection region and is arrange between the cell array region and the second recess, and vertical lines which are formed on the upper surface of the electrode exposed by the first recess.
Abstract translation: 提供了一种3D非易失性存储器件及其制造方法。 3D非易失性存储器件包括其中限定了单元阵列区域和连接区域的基板，形成在单元阵列区域和连接区域上并且包括堆叠电极的电极结构，形成在电极结构上的第二凹部 连接区域，形成在连接区域的电极结构上并且布置在电池阵列区域和第二凹部之间的第一凹部以及形成在由第一凹部暴露的电极的上表面上的垂直线。
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公开(公告)号：KR1020080050811A
公开(公告)日：2008-06-10
申请号：KR1020060121576
申请日：2006-12-04
Applicant: 삼성전자주식회사
Inventor： 임지운
IPC: H01L27/115
CPC classification number: H01L27/11519 , H01L21/265 , H01L21/823468 , H01L27/11521 , H01L27/2463
Abstract: A nonvolatile memory device and a method for manufacturing the same are provided to improve the reliability of the nonvolatile memory device by preventing the characteristic degradation of a cell due to silicide process. A common source region(260) is formed on a semiconductor substrate(100) to be extended to a first direction. A contact formation region(C) is defined on the common source region. A pair of floating gates(220) are formed to partially overlap the common source region with a second direction crossing the first direction. A control gate(250) is insulated along another wall of the floating gate from an upper portion of the floating gate to a direction opposite to the common source region. The control gate is extended to the first direction. A silicide blocking layer(310) is extended to the first direction on the common source region, so that blocks the common source region but opens the contact formation region. A silicide blocking spacer(320) is formed at a side of the silicide blocking layer. A contact(420) is formed on the silicide layer of the contact formation region.
Abstract translation: 提供一种非易失性存储器件及其制造方法，用于通过防止由硅化物处理引起的电池的特性劣化来提高非易失性存储器件的可靠性。 公共源极区域（260）形成在半导体衬底（100）上以延伸到第一方向。 接触形成区域（C）被限定在公共源极区域上。 一对浮动栅极（220）形成为与第一方向交叉的第二方向部分地重叠共用源极区域。 控制栅极（250）沿浮动栅极的另一个壁从浮动栅极的上部绝缘到与公共源极区域相反的方向。 控制门延伸到第一个方向。 硅化物阻挡层（310）在公共源极区域上延伸到第一方向，从而阻挡公共源极区域，但是打开接触形成区域。 硅化物阻挡层（320）形成在硅化物阻挡层的一侧。 在接触形成区域的硅化物层上形成接触（420）。
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