公开(公告)号：KR1020110083858A

公开(公告)日：2011-07-21

申请号：KR1020100003813

申请日：2010-01-15

Applicant: 삼성전자주식회사

Inventor： 현성우 ,  이병찬 ,  이선길 ,  손용훈

IPC: H01L27/108 ,  H01L21/8242

CPC classification number: H01L21/76224 ,  H01L27/1052 ,  H01L27/10876

Abstract: PURPOSE: A method for forming a semiconductor cell array area, a method for manufacturing a semiconductor device including the same, and a method for forming a semiconductor module including the semiconductor device are provided to stably secure an active area from a semiconductor plate by minimizing the influence of a semiconductor manufacturing process on an interface. CONSTITUTION: A semiconductor layer(20) is patterned to a plurality of particles. The plurality of particles are insulated on a semiconductor plate(10). Semiconductor pillars are formed on the semiconductor plate. The semiconductor plate has the materials which are different from the semiconductor layer. The semiconductor plate does not have oxygen elements.

Abstract translation: 目的：提供一种形成半导体单元阵列区域的方法，包括该半导体单元阵列区域的半导体器件的制造方法以及包括该半导体器件的半导体模块的形成方法，通过使半导体板的有源区域最小化 半导体制造工艺对界面的影响。 构成：将半导体层（20）图案化成多个颗粒。 多个颗粒在半导体板（10）上绝缘。 半导体柱形成在半导体板上。 半导体板具有与半导体层不同的材料。 半导体板不具有氧元素。

公开(公告)号：KR1020110100958A

公开(公告)日：2011-09-15

申请号：KR1020100020062

申请日：2010-03-05

Applicant: 삼성전자주식회사

Inventor： 손용훈 ,  정진하 ,  김중호 ,  우라자에브블라디미르 ,  강종혁 ,  현성우

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L21/20 ,  H01L21/28273 ,  H01L21/76838 ,  H01L27/0688 ,  H01L27/11578 ,  H01L27/11582

Abstract: 본 발명의 수직형 반도체 소자의 제조 방법은 기판 상에 기판 상부를 노출하는 개구부를 포함하는 적층체 구조물을 형성하는 것을 포함한다. 적층체 구조물의 개구부 내의 일부 영역에 제1 예비 반도체층을 형성한다. 제1 예비 반도체층을 1차로 상전이시켜 개구부 내의 일부 영역에 제1 단결정 반도체층을 형성한다. 제1 단결정 반도체층 상에 제2 예비 반도체층을 형성한다. 제2 예비 반도체층을 2차로 상전이시켜 제2 단결정 반도체층을 형성함으로써 제1 단결정 반도체층 및 제2 단결정 반도체층을 합체하여 단결정 반도체층을 형성하는 것을 포함한다.

公开(公告)号：KR1020100095900A

公开(公告)日：2010-09-01

申请号：KR1020090014942

申请日：2009-02-23

Applicant: 삼성전자주식회사

Inventor： 현성우 ,  최혜란 ,  이종욱 ,  손용훈 ,  김중호

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L21/28282 ,  H01L21/31051 ,  H01L21/31144 ,  H01L21/76877 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66833

Abstract: PURPOSE: A method for manufacturing a vertical nonvolatile memory device is provided to control the profile of source/drain regions by controlling the thickness of insulation layers arranged on the outermost and lowermost parts thereof. CONSTITUTION: Semiconductor patterns(120), insulation layers, gate patterns, and opening units are formed on a substrate. The semiconductor patterns are vertically formed on the substrate. The insulation layers and the gate patterns are alternatively laminated on the substrate to surround the semiconductor patterns. The opening units penetrate through the insulation layers to expose the substrate. Ions are implanted to the substrate exposed by the openings and the upper side of each semiconductor pattern. Source/drain regions(140,142) are formed on the upper and lower sides of each semiconductor pattern with a thermal process.

Abstract translation: 目的：提供一种用于制造垂直非易失性存储器件的方法，通过控制布置在其最外侧和最下部的绝缘层的厚度来控制源/漏区的轮廓。 构成：在衬底上形成半导体图案（120），绝缘层，栅极图案和开口单元。 在衬底上垂直形成半导体图形。 绝缘层和栅极图案交替层压在基板上以包围半导体图案。 开口单元穿过绝缘层以暴露基板。 离子被植入到由开口和每个半导体图案的上侧暴露的衬底上。 源极/漏极区域（140,142）通过热处理形成在每个半导体图案的上侧和下侧。

公开(公告)号：KR1020130118103A

公开(公告)日：2013-10-29

申请号：KR1020120041032

申请日：2012-04-19

Applicant: 삼성전자주식회사

Inventor： 현성우 ,  이선길

IPC: H01L21/336 ,  H01L21/265 ,  H01L21/20 ,  H01L29/78

CPC classification number: H01L21/823807 ,  H01L21/02362 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/1054 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/66545

Abstract: PURPOSE: A semiconductor device and a manufacturing method thereof are provided to prevent pre-halo ions from being diffused from a semiconductor substrate to a second epitaxial layer by forming a first epitaxial layer after the pre-halo ions are injected. CONSTITUTION: Pre-halo ions are injected to a semiconductor substrate (100). A first epitaxial layer (200) is formed on the front surface of the semiconductor substrate by epitaxial growth. A second epitaxial layer (300) is formed on the front surface of the first epitaxial layer by epitaxial growth. A device isolation layer (400) passing through the second epitaxial layer is formed. The first epitaxial layer prevents the pre-halo ions from being diffused from the semiconductor substrate to the second epitaxial layer.

Abstract translation: 目的：提供一种半导体器件及其制造方法，用于通过在注入预卤素离子之后形成第一外延层来防止预卤素离子从半导体衬底扩散到第二外延层。 构成：将预卤素离子注入到半导体衬底（100）中。 通过外延生长在半导体衬底的前表面上形成第一外延层（200）。 通过外延生长在第一外延层的前表面上形成第二外延层（300）。 形成穿过第二外延层的器件隔离层（400）。 第一外延层防止预卤素离子从半导体衬底扩散到第二外延层。

公开(公告)号：KR1020120019211A

公开(公告)日：2012-03-06

申请号：KR1020100082478

申请日：2010-08-25

Applicant: 삼성전자주식회사

Inventor： 현성우 ,  신유균 ,  이선길 ,  윤홍식

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L27/088 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/1079

Abstract: PURPOSE: A method for manufacturing a semiconductor device is provided to prevent a semiconductor substrate on a first semiconductor device area from being etched by forming a first etch stop layer in an inner wall of a first trench and a first gate structure of a first semiconductor device area. CONSTITUTION: A first semiconductor device area and a second semiconductor device area are defined on a semiconductor substrate(100). A first gate structure(200) is formed on the first semiconductor device area. A second gate structure(300) is formed on the second semiconductor device area. A first trench(113) is formed on both sides of the first gate structure. A second trench(116) is formed on both sides of the second gate structure.

Abstract translation: 目的：提供一种用于制造半导体器件的方法，以通过在第一沟槽的内壁和第一半导体器件的第一栅极结构中形成第一蚀刻停止层来防止第一半导体器件区域上的半导体衬底被蚀刻 区。 构成：在半导体衬底（100）上限定第一半导体器件区域和第二半导体器件区域。 第一栅极结构（200）形成在第一半导体器件区域上。 第二栅极结构（300）形成在第二半导体器件区域上。 第一沟槽（113）形成在第一栅极结构的两侧。 第二沟槽（116）形成在第二栅极结构的两侧。

公开(公告)号：KR1020110037340A

公开(公告)日：2011-04-13

申请号：KR1020090094743

申请日：2009-10-06

Applicant: 삼성전자주식회사

Inventor： 현성우 ,  이종욱 ,  손용훈 ,  전상훈 ,  강종혁 ,  김중호

IPC: G11C16/34 ,  G11C16/24 ,  G11C16/02

CPC classification number: G11C16/3468 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/11551

Abstract: PURPOSE: A three dimensional semiconductor memory device and a method of operating the same are provided to improve the uniformity of data by suppressing program disturbance. CONSTITUTION: In a three dimensional semiconductor memory device and a method of operating the same, a 3D semiconductor memory device comprises a plurality of strings. A plurality of strings interlinks a common source line and bit lines. Each string comprises a top alternative structure and a memory structure. The top alternative structure comprises a plurality of string selection transistors. The memory structure comprises a plurality of memory cell transistors. The selected string is connected to the selected bit line. Non-selected strings are electrically separated from the bit lines.

Abstract translation: 目的：提供三维半导体存储器件及其操作方法，以通过抑制程序干扰来提高数据的均匀性。 构成：在三维半导体存储器件及其操作方法中，3D半导体存储器件包括多个串。 多个串将公共源极线和位线相互连接。 每个字符串包括顶部替代结构和存储器结构。 顶部替代结构包括多个串选择晶体管。 存储器结构包括多个存储单元晶体管。 所选字符串连接到所选位线。 未选择的串与位线电分离。

公开(公告)号：KR101675388B1

公开(公告)日：2016-11-11

申请号：KR1020100082478

申请日：2010-08-25

Applicant: 삼성전자주식회사

Inventor： 현성우 ,  신유균 ,  이선길 ,  윤홍식

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L27/088 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: 본발명은반도체장치의제조방법에관한것이다. 본발명의일 실시예에따른반도체장치의제조방법은, 제1 반도체소자영역및 제2 반도체소자영역이정의된반도체기판을제공하고, 상기제1 반도체소자영역에제1 게이트구조물을형성하고, 상기제2 반도체소자영역에제2 게이트구조물을형성하고, 상기제1 게이트구조물의양측에제1 트렌치를형성하고, 상기제2 게이트구조물의양측에제2 트렌치를형성하고, 상기제1 트렌치내에제1 반도체패턴을형성하고, 상기제2 트렌치내에제2 반도체패턴을형성하는것을포함하되, 상기제1 및제2 게이트구조물의수직방향과나란한방향으로자른제1 및제2 트렌치의단면형상은서로다른형상을갖는다.

公开(公告)号：KR101597686B1

公开(公告)日：2016-02-25

申请号：KR1020090105412

申请日：2009-11-03

Applicant: 삼성전자주식회사

Inventor： 현성우 ,  이병찬 ,  이선길

IPC: H01L21/336 ,  H01L21/027

CPC classification number: H01L27/11578 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11575

Abstract: 3차원구조의반도체장치및 그제조방법이제공된다. 3차원반도체장치의제조방법은셀 어레이영역및 콘택영역을포함하는기판을준비하고, 기판상에, 하부분리영역에의해수평적으로분리된희생막패턴들및 희생막패턴들상에차례로적층된희생막들을포함하는박막구조체를형성하고, 박막구조체를관통하여셀 어레이영역의하부분리영역을노출시키는개구부를형성하는것을포함하되, 하부분리영역은셀 어레이영역및 콘택영역을가로지르고, 개구부는상기셀 어레이영역내에한정적으로형성된다.

公开(公告)号：KR1020110048719A

公开(公告)日：2011-05-12

申请号：KR1020090105412

申请日：2009-11-03

Applicant: 삼성전자주식회사

Inventor： 현성우 ,  이병찬 ,  이선길

IPC: H01L21/336 ,  H01L21/027

CPC classification number: H01L27/11578 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11575 ,  G03F7/70416

Abstract: PURPOSE: A three dimensional semiconductor memory device and a method of fabricating the same are provided to prevent disturbance in reading data from a selected cell string by selectively applying voltage to ground selection lines. CONSTITUTION: In a three dimensional semiconductor memory device and a method of fabricating the same, an insulating layer(121) and a sacrificial layer pattern(131) are formed on a substrate(10). The substrate comprises a cell array area, a peripheral circuit area and a contact area. After the sacrificial layer pattern forms a sacrificing layer on the insulating layer, the sacrificing layer is patterned. A reserved separation pattern(20) is formed between sacrificial layer patterns. The reserved separation pattern is formed by the sacrificial layer pattern and an insulating material having etching selectivity.

Abstract translation: 目的：提供三维半导体存储器件及其制造方法，以通过选择性地向地选择线施加电压来防止从所选单元串读取数据的干扰。 构成：在三维半导体存储器件及其制造方法中，在衬底（10）上形成绝缘层（121）和牺牲层图案（131）。 基板包括单元阵列区域，外围电路区域和接触区域。 在牺牲层图案在绝缘层上形成牺牲层之后，对牺牲层进行图案化。 在牺牲层图案之间形成预留分离图案（20）。 保留的分离图案由牺牲层图案和具有蚀刻选择性的绝缘材料形成。

公开(公告)号：KR1020100099912A

公开(公告)日：2010-09-15

申请号：KR1020090018485

申请日：2009-03-04

Applicant: 삼성전자주식회사

Inventor： 손용훈 ,  이종욱 ,  김중호 ,  현성우

IPC: H01L21/336

CPC classification number: H01L27/108 ,  H01L27/10802 ,  H01L27/10844

Abstract: PURPOSE: A semiconductor memory device and a manufacturing method thereof are provided to improve the degree of integration by forming a conductive line applying voltage to the source area of the gate pattern bottom. CONSTITUTION: An active pillar(11) is formed to protruding from a semiconductor substrate(1). A gate pattern(18a) comprises a gate insulation layer(16) on one side of the active pillar. A conductive line(23a) contacts at least one side of the active pillar under the gate pattern. A drain region(11c) is formed on the active pillar on the gate pattern.

Abstract translation: 目的：提供半导体存储器件及其制造方法，以通过形成向栅极图案底部的源极区域施加电压的导电线来提高积分度。 构成：形成有源柱（11）从半导体衬底（1）突出。 栅极图案（18a）包括在有源支柱的一侧上的栅绝缘层（16）。 导线（23a）在栅极图案下接触有源支柱的至少一侧。 漏极区域（11c）形成在栅极图案上的有源支柱上。