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公开(公告)号：KR1020100061290A
公开(公告)日：2010-06-07
申请号：KR1020090038461
申请日：2009-04-30
Applicant: 삼성전자주식회사 , 성균관대학교산학협력단
IPC: H01L29/786
CPC classification number: H01L27/1225 , H01L27/092 , H01L27/1251
Abstract: PURPOSE: A semiconductor device and a manufacturing method thereof are provided to improve a performance characteristic of the device by reducing a resistance with forming a p+ domain on the central part of a first oxide channel layer. CONSTITUTION: A first oxide channel layer(C10) is formed into a first conductive type oxide on a lower part layer. A first electrode layer covering the first channel layer is formed on the lower part layer. The first electrode layer and a second electrode layer separated are formed. A second oxide channel layer(C20) is formed into a second conductive type oxide on the lower part later. The first electrode layer is patterned. A first source, a first drain and the second drain are formed by the patterning of the first electrode layer.
Abstract translation: 目的：提供半导体器件及其制造方法，以通过在第一氧化物沟道层的中心部分形成p +畴来降低电阻来提高器件的性能特性。 构成：第一氧化物沟道层（C10）在下部层上形成为第一导电型氧化物。 覆盖第一沟道层的第一电极层形成在下部层上。 形成分离的第一电极层和第二电极层。 第二氧化物沟道层（C20）稍后在下部形成第二导电型氧化物。 图案化第一电极层。 通过图案化第一电极层形成第一源极，第一漏极和第二漏极。
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公开(公告)号：KR1020100040580A
公开(公告)日：2010-04-20
申请号：KR1020080099778
申请日：2008-10-10
Applicant: 삼성전자주식회사 , 성균관대학교산학협력단
IPC: H01L21/8239
CPC classification number: G11C5/02 , G11C5/143 , G11C7/18 , G11C8/12 , G11C13/0023 , G11C2213/71
Abstract: PURPOSE: A stacked memory device is provided to reduce the area in which the stacked memory device is occupied by stacking active circuit parts between memory layers. CONSTITUTION: Stacked memory layers(110) include memory cell array. A first active circuit part(140) processes the address information of the memory cell array which is divided into vertical address information and horizontal address information. A second active circuit part(160) is arranged on the first active circuit part. The second active circuit part generates memory selection signal to each memory cell based on the processed signal of the first active circuit parts. The first active circuit part includes a level decoder(120) and a pre decoder(130). The level decoder decodes the vertical address information. The pre decoder decodes the horizontal address information.
Abstract translation: 目的：提供堆叠的存储器件，以通过在存储器层之间堆叠有源电路部分来减少堆叠的存储器件被占用的区域。 构成：堆叠的存储器层（110）包括存储单元阵列。 第一有源电路部分（140）处理被划分为垂直地址信息和水平地址信息的存储单元阵列的地址信息。 第二有源电路部分（160）布置在第一有源电路部分上。 第二有源电路部分基于第一有源电路部分的处理信号，向每个存储器单元产生存储器选择信号。 第一有源电路部分包括电平解码器（120）和预解码器（130）。 电平解码器解码垂直地址信息。 预解码器解码水平地址信息。
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公开(公告)号：KR101413658B1
公开(公告)日：2014-07-07
申请号：KR1020090038461
申请日：2009-04-30
Applicant: 삼성전자주식회사 , 성균관대학교산학협력단
IPC: H01L29/786
Abstract: 반도체 소자 및 그 제조방법에 관해 개시되어 있다. 개시된 반도체 소자는 p형 산화물 박막트랜지스터 및 n형 산화물 박막트랜지스터를 포함하는 상보성(complementary) 소자일 수 있다. 예컨대, 개시된 반도체 소자는 인버터(inverter), NAND 소자, NOR 소자 등과 같은 논리소자일 수 있다.
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公开(公告)号：KR101413657B1
公开(公告)日：2014-07-02
申请号：KR1020080119942
申请日：2008-11-28
Applicant: 삼성전자주식회사 , 성균관대학교산학협력단
IPC: H01L29/786
Abstract: 반도체 소자 및 그 제조방법에 관해 개시되어 있다. 개시된 반도체 소자는 p형 산화물 박막트랜지스터 및 n형 산화물 박막트랜지스터를 포함하는 상보성(complementary) 소자일 수 있다. 예컨대, 개시된 반도체 소자는 인버터(inverter), NAND 소자, NOR 소자 등과 같은 논리소자일 수 있다.
Abstract translation: 公开了一种半导体器件及其制造方法。 所公开的半导体器件可以是包括p型氧化物薄膜晶体管和n型氧化物薄膜晶体管的互补装置。 例如，所公开的半导体器件可以是诸如反相器，NAND器件，NOR器件等的逻辑器件。
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公开(公告)号：KR101636906B1
公开(公告)日：2016-07-07
申请号：KR1020090131298
申请日：2009-12-24
Applicant: 삼성전자주식회사 , 성균관대학교산학협력단
Abstract: 디스플레이장치의전력소비를감소시킬수 있는게이트구동장치및 게이트구동방법이개시된다. 개시된게이트구동장치및 게이트구동방법은, 이전의화소행을선택한후에다음의화소행을선택하는동안, 이전의화소행으로부터방전되는전류를다음의화소행에제공한다. 따라서, 이전의화소행에서버려지는전류를다음의화소행에서재활용할수 있으며, 각각의화소행을선택하기위하여필요한전류를감소시킬수 있다. 그결과, 개시된게이트구동장치및 게이트구동방법을채용한디스플레이장치는소비전력이전반적으로감소할수 있다.
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Patent Agency Ranking
公开(公告)号：KR1020110074361A
公开(公告)日：2011-06-30
申请号：KR1020090131298
申请日：2009-12-24
Applicant: 삼성전자주식회사 , 성균관대학교산학협력단
Abstract: PURPOSE: A gate driving device and a gate driving method are provided to recycle a next pixel row by providing current discharged from a previous pixel row for the next pixel column. CONSTITUTION: A plurality of shifts(101,102,103,104) include a set signal input terminal, a first clock input terminal, a second clock input terminal, and an output terminal. A plurality of switches transfer the residual current discharged from each shift to the output of the other shift. A switch control unit(120) controls switching operations of a plurality of switches. A clock generator(110) generates a plurality of clocks to be inputted into the first clock input terminal and the second clock input terminal. The clock generator repeatedly generates sequentially three phase-shifted clock signals.
Abstract translation: 目的：提供一种栅极驱动装置和栅极驱动方法，用于通过从下一像素列的先前像素行排出的电流来再循环下一个像素行。 构成：多个位移（101,102,103,104）包括设定信号输入端子，第一时钟输入端子，第二时钟输入端子和输出端子。 多个开关将从每个移位放电的剩余电流传送到另一个移位的输出。 开关控制单元（120）控制多个开关的开关动作。 时钟发生器（110）产生要输入到第一时钟输入端和第二时钟输入端的多个时钟。 时钟发生器反复产生三个相移时钟信号。
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公开(公告)号：KR1020100061064A
公开(公告)日：2010-06-07
申请号：KR1020080119942
申请日：2008-11-28
Applicant: 삼성전자주식회사 , 성균관대학교산학협력단
IPC: H01L29/786
CPC classification number: H01L27/1225 , H01L21/8238 , H01L27/092 , H01L27/1251
Abstract: PURPOSE: A semiconductor device and a manufacturing method thereof are provided to easily form as a low-temperature process by forming a first oxide channel layer and a second oxide channel layer into an oxide. CONSTITUTION: A first thin film transistor includes a first source(S10), a first drain, a first channel layer, and a first gate. A second thin film transistor includes a second source(S20), a second drain, a second channel layer, and a second gate. One is a p-type oxide layer among the first and the second channel layer. The first and the second thin film transistor is a bottom gate(BG10, BG20) structure or a top gate structure. One is a dual gate including more other gates among the first and the second thin film transistor at least.
Abstract translation: 目的：通过将第一氧化物沟道层和第二氧化物沟道层形成为氧化物，提供半导体器件及其制造方法以容易地形成为低温工艺。 构成：第一薄膜晶体管包括第一源（S10），第一漏极，第一沟道层和第一栅极。 第二薄膜晶体管包括第二源（S20），第二漏极，第二沟道层和第二栅极。 一个是第一和第二沟道层中的p型氧化物层。 第一和第二薄膜晶体管是底栅（BG10，BG20）结构或顶栅结构。 一个是至少包括第一和第二薄膜晶体管中的更多其它栅极的双栅极。
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公开(公告)号：KR1020090084236A
公开(公告)日：2009-08-05
申请号：KR1020080010291
申请日：2008-01-31
Applicant: 삼성전자주식회사 , 성균관대학교산학협력단
Abstract: A memory chip array is provided to reduce the whole size by arranging a circuit related to column operation such as a sense amplifier and a column decoder. A memory chip array comprises a plurality of cell arrays(20) and a row decoder. The row decoder comprises a low select(22) and a pre-decoder(21), and the low select is formed in one-side of each cell array. A plurality of cell arrays are connected to pre-decoder in common, and the sense amplifier and the column decoder(23) are formed in the lower-part of each cell array.
Abstract translation: 提供存储器芯片阵列以通过布置与诸如读出放大器和列解码器的列操作相关的电路来减小整体尺寸。 存储芯片阵列包括多个单元阵列（20）和行解码器。 行解码器包括低选择（22）和预解码器（21），并且低选择形成在每个单元阵列的一侧。 多个单元阵列共同连接到预解码器，并且读出放大器和列解码器（23）形成在每个单元阵列的下部。
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公开(公告)号：KR101929941B1
公开(公告)日：2018-12-18
申请号：KR1020120087993
申请日：2012-08-10
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
Abstract: 저항 변화 물질 소자 및 이를 적용한 디바이스가 개시된다. 개시된 저항 변화 물질 소자는, 제1및 제2전극 사이에 위치되는 저항 변화 물질층을 구비한다. 제1및 제2전극 중 어느 한 전극과 저항 변화 물질층 사이에는 자가 정류층이 마련된다.
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