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    반도체 소자 및 그 제조방법
    1.
    发明公开
    반도체 소자 및 그 제조방법 有权
    半导体器件及其制造方法

    公开(公告)号：KR1020100061064A

    公开(公告)日：2010-06-07

    申请号：KR1020080119942

    申请日：2008-11-28

    Applicant: 삼성전자주식회사 ,  성균관대학교산학협력단

    Inventor： 박재철 ,  송이헌 ,  박영수 ,  권기원 ,  김창정 ,  김경국 ,  박성호 ,  이성훈 ,  김상욱 ,  김선일

    IPC: H01L29/786

    CPC classification number: H01L27/1225 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/1251

    Abstract: PURPOSE: A semiconductor device and a manufacturing method thereof are provided to easily form as a low-temperature process by forming a first oxide channel layer and a second oxide channel layer into an oxide. CONSTITUTION: A first thin film transistor includes a first source(S10), a first drain, a first channel layer, and a first gate. A second thin film transistor includes a second source(S20), a second drain, a second channel layer, and a second gate. One is a p-type oxide layer among the first and the second channel layer. The first and the second thin film transistor is a bottom gate(BG10, BG20) structure or a top gate structure. One is a dual gate including more other gates among the first and the second thin film transistor at least.

    Abstract translation: 目的：通过将第一氧化物沟道层和第二氧化物沟道层形成为氧化物，提供半导体器件及其制造方法以容易地形成为低温工艺。 构成：第一薄膜晶体管包括第一源（S10），第一漏极，第一沟道层和第一栅极。 第二薄膜晶体管包括第二源（S20），第二漏极，第二沟道层和第二栅极。 一个是第一和第二沟道层中的p型氧化物层。 第一和第二薄膜晶体管是底栅（BG10，BG20）结构或顶栅结构。 一个是至少包括第一和第二薄膜晶体管中的更多其它栅极的双栅极。

    반도체 소자 및 그 제조방법
    4.
    发明公开
    반도체 소자 및 그 제조방법 有权
    半导体器件及其制造方法

    公开(公告)号：KR1020100061290A

    公开(公告)日：2010-06-07

    申请号：KR1020090038461

    申请日：2009-04-30

    Applicant: 삼성전자주식회사 ,  성균관대학교산학협력단

    Inventor： 박재철 ,  송이헌 ,  박영수 ,  김창정 ,  김경국 ,  박성호 ,  이성훈 ,  김상욱 ,  김선일 ,  권기원

    IPC: H01L29/786

    CPC classification number: H01L27/1225 ,  H01L27/092 ,  H01L27/1251

    Abstract: PURPOSE: A semiconductor device and a manufacturing method thereof are provided to improve a performance characteristic of the device by reducing a resistance with forming a p+ domain on the central part of a first oxide channel layer. CONSTITUTION: A first oxide channel layer(C10) is formed into a first conductive type oxide on a lower part layer. A first electrode layer covering the first channel layer is formed on the lower part layer. The first electrode layer and a second electrode layer separated are formed. A second oxide channel layer(C20) is formed into a second conductive type oxide on the lower part later. The first electrode layer is patterned. A first source, a first drain and the second drain are formed by the patterning of the first electrode layer.

    Abstract translation: 目的：提供半导体器件及其制造方法，以通过在第一氧化物沟道层的中心部分形成p +畴来降低电阻来提高器件的性能特性。 构成：第一氧化物沟道层（C10）在下部层上形成为第一导电型氧化物。 覆盖第一沟道层的第一电极层形成在下部层上。 形成分离的第一电极层和第二电极层。 第二氧化物沟道层（C20）稍后在下部形成第二导电型氧化物。 图案化第一电极层。 通过图案化第一电极层形成第一源极，第一漏极和第二漏极。

    적층 메모리 소자
    5.
    发明公开
    적층 메모리 소자 无效
    堆叠存储器件

    公开(公告)号：KR1020100040580A

    公开(公告)日：2010-04-20

    申请号：KR1020080099778

    申请日：2008-10-10

    Applicant: 삼성전자주식회사 ,  성균관대학교산학협력단

    Inventor： 박재철 ,  권기원 ,  송이헌 ,  박영수 ,  김창정 ,  김상욱 ,  김선일

    IPC: H01L21/8239

    CPC classification number: G11C5/02 ,  G11C5/143 ,  G11C7/18 ,  G11C8/12 ,  G11C13/0023 ,  G11C2213/71

    Abstract: PURPOSE: A stacked memory device is provided to reduce the area in which the stacked memory device is occupied by stacking active circuit parts between memory layers. CONSTITUTION: Stacked memory layers(110) include memory cell array. A first active circuit part(140) processes the address information of the memory cell array which is divided into vertical address information and horizontal address information. A second active circuit part(160) is arranged on the first active circuit part. The second active circuit part generates memory selection signal to each memory cell based on the processed signal of the first active circuit parts. The first active circuit part includes a level decoder(120) and a pre decoder(130). The level decoder decodes the vertical address information. The pre decoder decodes the horizontal address information.

    Abstract translation: 目的：提供堆叠的存储器件，以通过在存储器层之间堆叠有源电路部分来减少堆叠的存储器件被占用的区域。 构成：堆叠的存储器层（110）包括存储单元阵列。 第一有源电路部分（140）处理被划分为垂直地址信息和水平地址信息的存储单元阵列的地址信息。 第二有源电路部分（160）布置在第一有源电路部分上。 第二有源电路部分基于第一有源电路部分的处理信号，向每个存储器单元产生存储器选择信号。 第一有源电路部分包括电平解码器（120）和预解码器（130）。 电平解码器解码垂直地址信息。 预解码器解码水平地址信息。

    비휘발성 메모리의 동작 방법
    6.
    发明公开
    비휘발성 메모리의 동작 방법 有权
    非易失性存储器的操作方法

    公开(公告)号：KR1020100038714A

    公开(公告)日：2010-04-15

    申请号：KR1020080097786

    申请日：2008-10-06

    Applicant: 삼성전자주식회사 ,  성균관대학교산학협력단

    Inventor： 안승언 ,  권기원 ,  박재철 ,  박영수 ,  이명재

    IPC: G11C16/34 ,  G11C16/08 ,  G11C16/10

    CPC classification number: G11C8/06 ,  G06F12/0238 ,  G06F2212/7201 ,  G11C13/0069

    Abstract: PURPOSE: An operation method of a nonvolatile memory is provided to improve the reliability of a nonvolatile memory status by transiting the state of a nonvolatile memory to only one side direction. CONSTITUTION: The first logical address and the first physical address are written in the specific row of a look-up table(LUT). First data is programmed in data storage area which the first physical address points the first logical address(LA) is mapped. A first logical address and a second physical address(PA) are written in the other row of the look-up table. Second data is programmed in data storage area which the second physical address points.

    Abstract translation: 目的：提供一种非易失性存储器的操作方法，以通过将非易失性存储器的状态转换为仅一个侧面方向来提高非易失性存储器状态的可靠性。 构成：第一个逻辑地址和第一个物理地址被写入查找表（LUT）的特定行。 第一数据被编程在数据存储区域中，第一物理地址指向第一逻辑地址（LA）被映射。 第一逻辑地址和第二物理地址（PA）被写入查找表的另一行。 第二数据被编程在第二物理地址指向的数据存储区中。

    반도체 소자 및 그 제조방법
    8.
    发明授权
    반도체 소자 및 그 제조방법 有权
    半导体装置及其制造方法

    公开(公告)号：KR101413657B1

    公开(公告)日：2014-07-02

    申请号：KR1020080119942

    申请日：2008-11-28

    Applicant: 삼성전자주식회사 ,  성균관대학교산학협력단

    Inventor： 박재철 ,  송이헌 ,  박영수 ,  권기원 ,  김창정 ,  김경국 ,  박성호 ,  이성훈 ,  김상욱 ,  김선일

    IPC: H01L29/786

    Abstract: 반도체 소자 및 그 제조방법에 관해 개시되어 있다. 개시된 반도체 소자는 p형 산화물 박막트랜지스터 및 n형 산화물 박막트랜지스터를 포함하는 상보성(complementary) 소자일 수 있다. 예컨대, 개시된 반도체 소자는 인버터(inverter), NAND 소자, NOR 소자 등과 같은 논리소자일 수 있다.

    Abstract translation: 公开了一种半导体器件及其制造方法。 所公开的半导体器件可以是包括p型氧化物薄膜晶体管和n型氧化物薄膜晶体管的互补装置。 例如，所公开的半导体器件可以是诸如反相器，NAND器件，NOR器件等的逻辑器件。

    적층 메모리 장치
    9.
    发明公开
    적층 메모리 장치 有权
    多层记忆体设备

    公开(公告)号：KR1020090027561A

    公开(公告)日：2009-03-17

    申请号：KR1020080047092

    申请日：2008-05-21

    Applicant: 삼성전자주식회사 ,  성균관대학교산학협력단

    Inventor： 박재철 ,  권기원 ,  박영수 ,  이승훈 ,  안승언

    IPC: G11C17/00 ,  H01L21/8239 ,  H01L23/12

    CPC classification number: G11C5/02 ,  G11C5/063 ,  G11C8/10 ,  G11C8/14

    Abstract: A multi-layered memory apparatus is provided to improve a data storage density by forming one or more memory layer by a plurality of sub arrays. A multi-layered memory apparatus includes two or more memory parts(12) and an active circuit part(11). The active circuit part includes a decoder, and is formed between the memory parts. The memory part includes one or more memory layer. The memory layer is a memory array of a cross point type, and has a plurality of sub arrays. The active circuit part is formed on a non-silicone substrate. The non-silicone substrate is made of plastic, glass, ceramic, oxide material, or nitride material.

    Abstract translation: 提供一种多层存储装置，通过由多个子阵列形成一个或多个存储层来提高数据存储密度。 多层存储装置包括两个或多个存储器部件（12）和有源电路部件（11）。 有源电路部分包括解码器，并且形成在存储器部分之间。 存储器部分包括一个或多个存储器层。 存储层是交叉点类型的存储器阵列，并且具有多个子阵列。 有源电路部分形成在非硅衬底上。 非硅树脂基材由塑料，玻璃，陶瓷，氧化物材料或氮化物材料制成。

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