公开(公告)号：KR1020140032186A

公开(公告)日：2014-03-14

申请号：KR1020120098767

申请日：2012-09-06

Applicant: 서울대학교산학협력단

Inventor： 박병국 ,  김형진 ,  김가람 ,  이정한 ,  권민우

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: G06N3/02 ,  G06N3/049 ,  G06N3/063 ,  G11C11/54 ,  H01L29/66825

Abstract: The present invention relates to a semiconductor device used as a core device for realizing a biomimetic calculation system. Provided are a low power synaptic semiconductor device and an operation method thereof. A long-term memory unit is formed in one side where a source, a drain, and a gate are not formed in the floating body of a semiconductor device formed as a short-term memory unit which is electrically isolated from a peripheral region. Thereby, the low power synaptic semiconductor device imitates not only the causality deduction property of a body due to the signal time difference of a neuron before/after a synapse and a short-term and long-term memory switching property but also the short-term memory of a biological nervous system according to impact ionization. [Reference numerals] (40) (1) Short-term memory element; (60) (2) Long-term memory element

Abstract translation: 本发明涉及用作实现仿生计算​​系统的核心装置的半导体装置。 提供了一种低功率突触半导体器件及其操作方法。 长期存储单元形成在源极，漏极和栅极未形成在形成为与周边区域电隔离的短期存储单元的半导体器件的浮动体中的一侧。 因此，低功率突触半导体器件不仅由于神经元在突触前后的信号时间差以及短期和长期记忆切换特性而且模拟短期和长期记忆切换特性，而且模仿身体的因果性推导特性 根据碰撞电离记录生物神经系统。 （附图标记）（40）（1）短期记忆元件; （60）（2）长期记忆元素

公开(公告)号：KR101091010B1

公开(公告)日：2011-12-08

申请号：KR1020100129644

申请日：2010-12-17

Applicant: 서울대학교산학협력단

Inventor： 박병국 ,  김가람

IPC: H01L27/108 ,  H01L21/8242 ,  H01L29/78 ,  H01L21/335

CPC classification number: H01L29/7827 ,  H01L27/10841 ,  H01L29/66666

Abstract: PURPOSE: A DRAM device with a single transistor structure for storing 2 bits is provided to store 2 bits per a cell by forming an impurity doping layer with the opposite polarity of a semiconductor body in the center of the semiconductor body. CONSTITUTION: An active area, which includes semiconductor bodies(13,17), is formed into a P-type semiconductor. A source(11) and a drain(19) are formed in the upper side and the down side of the semiconductor body. A gate(30) is formed on the side of the semiconductor body while being placed between gate insulating layers(20). An impurity doping layer(15), which has the opposite polarity of the semiconductor body, is formed in the center of the upper side and the down side of the semiconductor body. The impurity doping layer electrically disconnects the semiconductor body.

Abstract translation: 目的：提供具有用于存储2位的单晶体管结构的DRAM器件，以通过在半导体本体的中心形成具有与半导体本体相反极性的杂质掺杂层来存储每个单元的2位。 构成：包括半导体本体（13,17）的有源区域形成为P型半导体。 源极（11）和漏极（19）形成在半导体本体的上侧和下侧。 栅极（30）形成在半导体本体侧，同时放置在栅极绝缘层（20）之间。 在半导体本体的上侧和下侧的中心形成有具有与半导体本体相反的极性的杂质掺杂层（15）。 杂质掺杂层电连接半导体本体。

公开(公告)号：KR101425857B1

公开(公告)日：2014-07-31

申请号：KR1020120098767

申请日：2012-09-06

Applicant: 서울대학교산학협력단

Inventor： 박병국 ,  김형진 ,  김가람 ,  이정한 ,  권민우

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: G06N3/02 ,  G06N3/049 ,  G06N3/063

Abstract: 본 발명은 생체 모방 계산 시스템 구현에 핵심 소자로 사용되는 반도체 소자 및 그 동작방법에 관한 것으로, 주변과 전기적으로 고립되어 단기기억 수단으로 형성된 반도체 소자의 플로팅 바디에 소스, 드레인 및 게이트가 형성되지 않은 일측으로 장기기억 수단을 구비함으로써, 충격이온화에 따른 생체 신경계의 단기기억은 물론, 단-장기기억 전환 특성과 시냅스 전, 후 뉴런의 신호 시간차에 의한 생체의 인과관계 추론 특성을 모두 모방할 수 있는 저전력 시냅스 모방 반도체 소자 및 그 동작방법을 제공한다.

公开(公告)号：KR101147523B1

公开(公告)日：2012-05-21

申请号：KR1020100056777

申请日：2010-06-15

Applicant: 서울대학교산학협력단

Inventor： 박병국 ,  김가람

IPC: H01L27/108 ,  H01L21/8242

Abstract: 본 발명은 반도체 메모리 소자 및 이를 이용한 메모리 어레이에 관한 것으로, 더욱 상세하게는 커패시터 없이 하나의 트랜지스터로 스플릿게이트 구조를 갖는 1T 디램 소자 및 이를 이용한 디램 어레이에 관한 것이다.

公开(公告)号：KR101089659B1

公开(公告)日：2011-12-06

申请号：KR1020090049080

申请日：2009-06-03

Applicant: 서울대학교산학협력단

Inventor： 박병국 ,  김가람

IPC: H01L21/336 ,  H01L29/78

Abstract: 본 발명은 1T DRAM 메모리 셀 및 그 제조방법에 관한 것으로, 돌출된 바디를 형성하고 바디 일측에 적절한 하이 도핑을 함으로써, excess hole을 소스와 드레인으로부터 고립시켜 SRH recombination을 막을 수 있도록 하여, 1T DRAM이라도 종래보다 retention time을 2배 이상 향상시킬 수 있고, 높은 sensing margin의 확보는 물론 read 속도도 개선할 수 있게 된 효과가 있다.
돌출, 바디, 저장노드, 1T DRAM, 메모리 셀

公开(公告)号：KR1020140074722A

公开(公告)日：2014-06-18

申请号：KR1020120142998

申请日：2012-12-10

Applicant: 삼성전자주식회사 ,  서울대학교산학협력단

Inventor： 강동훈 ,  박병국 ,  손중곤 ,  김가람 ,  김장현 ,  박의환

IPC: H01L33/36 ,  H01L33/38

CPC classification number: H01L33/38 ,  H01L33/20

Abstract: The present invention relates to a semiconductor light emitting device, which comprises a first conductive semiconductor layer; an active layer formed on the first conductive semiconductor layer; a second conductive semiconductor layer formed on the active layer and having an upper surface on which at least one groove unit is formed; a transparent electrode layer formed on the second conductive semiconductor layer; and a first electrode and a second electrode electrically connected to the first conductive semiconductor layer and the second conductive semiconductor layer, wherein the center of the groove unit intersects with a straight line which links the center of the first electrode and the center of the second electrode to improve the current distribution, thereby improving the internal light extraction efficiency.

Abstract translation: 本发明涉及一种半导体发光器件，其包括第一导电半导体层; 形成在所述第一导电半导体层上的有源层; 形成在所述有源层上并具有上表面的第二导电半导体层，所述上表面上形成有至少一个沟槽单元; 形成在所述第二导电半导体层上的透明电极层; 以及电连接到第一导电半导体层和第二导电半导体层的第一电极和第二电极，其中，沟槽单元的中心与连接第一电极的中心和第二电极的中心的直线相交 提高电流分布，从而提高内部光提取效率。

公开(公告)号：KR1020110136640A

公开(公告)日：2011-12-21

申请号：KR1020100056777

申请日：2010-06-15

Applicant: 서울대학교산학협력단

Inventor： 박병국 ,  김가람

IPC: H01L27/108 ,  H01L21/8242

CPC classification number: H01L29/78645 ,  H01L27/108 ,  H01L29/42384

Abstract: PURPOSE: A 1T dram device with a split gate structure and a dram array using the same are provided to improve not only retention time of data '1' but also the retention time of data '0' by including one or two side gates in one side or either side to be separated from a center gate. CONSTITUTION: A semiconductor body is formed into a pillar shape. A source(20) and a drain are formed in the either side of the semiconductor body. A center gate(50) is formed on the semiconductor body between gate insulating layers. The center gate is connected to a center word line. Side gates(40,60) are formed on the semiconductor body between isolation insulating layers(32,34).

Abstract translation: 目的：提供具有分离栅极结构的1T电容器和使用其的电容阵列，以通过将一个或两个侧栅极包括在一个中来提高数据“1”的保留时间，而且还可以改善数据“0”的保留时间 侧或任一侧与中心门分离。 构成：将半导体体形成为柱状。 源极（20）和漏极形成在半导体本体的任一侧。 在栅极绝缘层之间的半导体本体上形成中心栅极（50）。 中心门连接到中心字线。 在隔离绝缘层（32,34）之间的半导体本体上形成侧栅极（40,60）。

公开(公告)号：KR1020100130407A

公开(公告)日：2010-12-13

申请号：KR1020090049080

申请日：2009-06-03

Applicant: 서울대학교산학협력단

Inventor： 박병국 ,  김가람

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L27/108 ,  H01L21/02225 ,  H01L21/2255 ,  H01L29/41725

Abstract: PURPOSE: A memory cell having a raised body for a storage node and a fabrication method of the same are provided to prevent SRH recombination by forming a protruded body and performing high doping on one side of the body. CONSTITUTION: A source(24) and a drain(28) are formed on a buried oxide of an SOI substrate and are separated from each other. A body region(26) is interposed between the source and the drain and is higher than them. The body region is protruded to be 1.5-2 times as high as the source and the drain. A gate(42) is formed on at least one side of the body region while having an insulating layer between the gate and the source. Two gates are formed at both ends of the body region and have the insulating layer between the two gates.

Abstract translation: 目的：提供具有用于存储节点的凸起体的记忆单元及其制造方法，以通过形成突出体并在身体的一侧执行高掺杂来防止SRH复合。 构成：在SOI衬底的掩埋氧化物上形成源极（24）和漏极（28），并且彼此分离。 主体区域（26）插入在源极和漏极之间并且高于它们。 体区域突出为源极和漏极的1.5-2倍。 栅极（42）形成在主体区域的至少一侧上，同时在栅极和源极之间具有绝缘层。 两个门形成在本体区域的两端，并且在两个门之间具有绝缘层。