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公开(公告)号：KR102077259B1
公开(公告)日：2020-02-13
申请号：KR1020170021679
申请日：2017-02-17
Applicant: 서울대학교산학협력단
IPC: C10L10/14 , C07C49/753
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公开(公告)号：KR101160585B1
公开(公告)日：2012-06-28
申请号：KR1020100073924
申请日：2010-07-30
Applicant: 서울대학교산학협력단
IPC: H01L29/78 , H01L21/336
Abstract: 본 발명은 트랜지스터 및 그 제조방법에 관한 것으로, 더욱 상세하게는 실리콘 기판 위에 탄소나노튜브(CNT)를 게이트로 이용하고 전기적으로 가상 소스/드레인을 형성함으로써, 상용 가능한 수 나노 미터의 채널 길이를 가지는 모스펫(MOSFET) 및 그 제조방법에 관한 것이다.
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公开(公告)号：KR1020120095739A
公开(公告)日：2012-08-29
申请号：KR1020110015243
申请日：2011-02-21
Applicant: 서울대학교산학협력단
IPC: H01L29/786
CPC classification number: H01L29/66765 , H01L21/32134 , H01L29/42384
Abstract: PURPOSE: A method for manufacturing a thin film transistor having a rounded gate is provided to prevent the generation of hump because an edge part of a gate electrode is rounded by an undercut phenomenon. CONSTITUTION: A first conductive film is evaporated on an insulation board(10). After the first conductive film is dry-etched, a wet-etching process is implemented for a constant time to form a gate(26). A gate insulation layer(40) is formed on the gate and the board. A semiconductor material is evaporated on the gate insulation layer. A source section(52), a drain section(54), and a channel section(56) are formed on the semiconductor material. A source electrode(72) and a drain electrode(74) are respectively formed on the source and the drain sections.
Abstract translation: 目的：提供一种用于制造具有圆形栅极的薄膜晶体管的方法，以防止由于栅极电极的边缘部分由于底切现象而变圆而产生隆起。 构成：第一导电膜在绝缘板（10）上蒸发。 在第一导电膜被干蚀刻之后，实施湿法蚀刻工艺一段时间以形成栅极（26）。 在栅极和电路板上形成栅极绝缘层（40）。 半导体材料在栅极绝缘层上蒸发。 源极部分（52），漏极部分（54）和沟道部分（56）形成在半导体材料上。 在源极和漏极部分上分别形成源极（72）和漏极（74）。
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公开(公告)号：KR101195544B1
公开(公告)日：2012-10-29
申请号：KR1020110015243
申请日：2011-02-21
Applicant: 서울대학교산학협력단
IPC: H01L29/786
Abstract: 본 발명은 박막 트랜지스터의 제조방법에 관한 것으로, 더욱 상세하게는 습식 식각시 발생되는 언더컷 현상을 적극 이용하여 게이트 전극의 에지 부분을 라운딩된 형태로 제작함으로써, 험프(hump)의 발생을 방지하고 동시에 온전류(on current)를 향상시킬 수 있는 에지 부분이 라운딩된 게이트를 갖는 박막 트랜지스터의 제조방법에 관한 것이다.
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Patent Agency Ranking
公开(公告)号：KR1020110136532A
公开(公告)日：2011-12-21
申请号：KR1020100056615
申请日：2010-06-15
Applicant: 서울대학교산학협력단
IPC: H01L27/092
Abstract: PURPOSE: A 1T DRAM(Dynamic Random Access Memory) device which includes two gates in a depressed body, an operation method thereof, and a manufacturing method for the same are provided to independently apply negative voltage to the gate which is not overlapped with a drain, thereby significantly increasing data retention time. CONSTITUTION: A semiconductor body(32) is electrically isolated and depressed. A depressed part of the semiconductor body is arranged as a trench shape. A gate insulating film(52) is arranged in the depressed part of the semiconductor body. A first gate(62) and second gate(64) are filled in the depressed part of the semiconductor body. A source(72) and drain(74) are arranged with an N-type impurity doping layer.
Abstract translation: 目的：提供一种包括凹陷体中的两个栅极的1T DRAM（动态随机存取存储器）装置及其操作方法及其制造方法，以独立地向不与漏极重叠的栅极施加负电压 ，从而显着增加数据保留时间。 构成：半导体本体（32）被电隔离和压制。 将半导体本体的凹部配置为沟槽状。 栅极绝缘膜（52）布置在半导体本体的凹陷部分中。 第一栅极（62）和第二栅极（64）填充在半导体主体的凹陷部分中。 源极（72）和漏极（74）配置有N型杂质掺杂层。
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公开(公告)号：KR101286707B1
公开(公告)日：2013-07-16
申请号：KR1020120052537
申请日：2012-05-17
Applicant: 서울대학교산학협력단 , 서강대학교산학협력단
IPC: H01L29/78 , H01L21/336
CPC classification number: H01L29/7855 , H01L29/66931 , H01L29/7311 , H01L29/7376
Abstract: PURPOSE: A tunneling field effect transistor having the FINFET structure of an independent dual gate and a fabrication method thereof are provided to increase the driving current without the loss of a separate area by forming a vertical dual gate structure which is electrically separated from both sides of a semiconductor pin. CONSTITUTION: A semiconductor substrate (10) includes a semiconductor pin (14) at a constant height. A p+ region (62) and an n+ region (64) are formed at both sides of the semiconductor substrate. The semiconductor pin is formed between the p+ region and the n+ region. A first gate (52) is formed between one side of the semiconductor pin and the n+ region. A second gate (54) is formed between the other side of the semiconductor pin and the p+ region. The material of the first gate is different from that of the second gate.
Abstract translation: 目的：提供具有独立双栅极的FINFET结构的隧道场效应晶体管及其制造方法，以通过形成垂直双栅极结构来增加驱动电流而不损失单独的面积，所述垂直双栅极结构与 半导体引脚。 构成：半导体衬底（10）包括恒定高度的半导体管脚（14）。 在半导体衬底的两侧形成有p +区域（62）和n +区域（64）。 半导体管脚形成在p +区域和n +区域之间。 第一栅极（52）形成在半导体引脚的一侧和n +区之间。 第二栅极（54）形成在半导体管脚的另一侧和p +区域之间。 第一栅极的材料与第二栅极的材料不同。
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公开(公告)号：KR101163711B1
公开(公告)日：2012-07-09
申请号：KR1020100056615
申请日：2010-06-15
Applicant: 서울대학교산학협력단
IPC: H01L27/092
Abstract: 본 발명은 커패시터가 없는 1T 디램 소자와 그 동작방법 및 제조방법에 관한 것으로, 함몰된 바디에 두개의 게이트를 갖는 구조를 함으로써, GIDL 현상을 이용한 쓰기 동작이 가능하여 종래 소자의 신뢰성 문제를 해결할 수 있음은 물론 드레인과 겹치지 않는 게이트에 음의 전압을 독립적으로 인가할 수 있어 데이터 "0"의 보유시간을 획기적으로 늘릴 수 있게 된 효과가 있다.
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公开(公告)号：KR101113885B1
公开(公告)日：2012-03-06
申请号：KR1020110015241
申请日：2011-02-21
Applicant: 서울대학교산학협력단
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L45/04 , G11C13/0004 , H01L45/1233 , H01L45/146
Abstract: PURPOSE: A two-bit resistance memory device using an inverted staggered thin film transistor structure is provided to improve integration by forming a source electrode and a drain electrode to be asymmetrical. CONSTITUTION: A gate electrode(10) is formed on an insulating substrate. A gate insulating layer(20) is formed on the gate electrode. An active layer(30) is formed on the gate insulating layer. A resistance variable layer(40) is formed on the active layer. A source electrode(50) and a drain electrode(60) are formed on the resistance variable layer.
Abstract translation: 目的：提供使用反交错薄膜晶体管结构的2位电阻存储器件，以通过将源电极和漏电极形成为不对称来提高积分。 构成：在绝缘基板上形成栅电极（10）。 栅极绝缘层（20）形成在栅电极上。 在栅绝缘层上形成有源层（30）。 在有源层上形成电阻变化层（40）。 源电极（50）和漏电极（60）形成在电阻变化层上。
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公开(公告)号：KR1020120012052A
公开(公告)日：2012-02-09
申请号：KR1020100073924
申请日：2010-07-30
Applicant: 서울대학교산학협력단
IPC: H01L29/78 , H01L21/336
CPC classification number: H01L51/0048 , H01L29/08 , H01L29/66045 , H01L51/102
Abstract: PURPOSE: A transistor which uses carbon nano-tubes for a gate and a manufacturing method thereof are provided to electrically arrange a virtual source/drain with a second gate, thereby solving a problem according to a short channel effect. CONSTITUTION: A carbon nano-tube is arranged on the semiconductor substrate while placing a first insulating film(32) between the carbon nano-tube and the semiconductor substrate. A first gate(42) uses the carbon nano-tube. A second gate(62) is formed on the first gate by placing a second insulating film(52) between the first gate and the second gate. The second gate is formed by covering the first gate. An impurity doping layer(22,24) for source/drain contact is arranged on both sides of the semiconductor substrate by placing the second gate between the doping layer and the semiconductor substrate.
Abstract translation: 目的：提供一种使用碳纳米管作为栅极的晶体管及其制造方法，以使第二栅极电连接虚拟源极/漏极，从而根据短沟道效应来解决问题。 构成：在碳纳米管和半导体衬底之间放置第一绝缘膜（32），在半导体衬底上布置碳纳米管。 第一个门（42）使用碳纳米管。 通过在第一栅极和第二栅极之间放置第二绝缘膜（52），在第一栅极上形成第二栅极（62）。 第二栅极通过覆盖第一栅极而形成。 通过将第二栅极放置在掺杂层和半导体衬底之间，用于源/漏接触的杂质掺杂层（22,24）布置在半导体衬底的两侧。
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