公开(公告)号：KR1020010017373A

公开(公告)日：2001-03-05

申请号：KR1019990032856

申请日：1999-08-11

Applicant: 전자부품연구원

Inventor： 강남기 ,  이우성 ,  임욱 ,  유찬세 ,  조현민 ,  윤종광 ,  최현석 ,  금병훈

IPC: H01L23/48

Abstract: PURPOSE: A multiple-line grid array package is provided to simplify a manufacturing process, by soldering a multiple line grid on a package body in which an input/output node is arranged. CONSTITUTION: A semiconductor chip(13) is built in a package body, and a plurality of input/output nodes(12) are arranged on an upper surface of the package body(10). A multiple line grid(20) is soldered to the input/output node of the package body. The multiple line grid has a substrate(23) of a non-conductive material, and has the same size as the package body. A hole is located in a one-to-one correspondence with the input/output node. A unit lead(22) is formed by filling and applying a conductive material in the hole and soldered to the input/output node.

Abstract translation: 目的：提供多行网格阵列封装，以通过将多行网格焊接在其中布置输入/输出节点的封装体上来简化制造过程。 构成：半导体芯片（13）内置在封装主体中，并且多个输入/输出节点（12）布置在封装主体（10）的上表面上。 多线栅格（20）被焊接到封装体的输入/输出节点。 多线栅格具有非导电材料的衬底（23），并且具有与封装主体相同的尺寸。 孔与输入/输出节点一一对应地设置。 通过在孔中填充并施加导电材料并焊接到输入/输出节点来形成单元引线（22）。

公开(公告)号：KR100306133B1

公开(公告)日：2001-11-01

申请号：KR1019990032856

申请日：1999-08-11

Applicant: 전자부품연구원

Inventor： 강남기 ,  이우성 ,  임욱 ,  유찬세 ,  조현민 ,  윤종광 ,  최현석 ,  금병훈

IPC: H01L23/48

Abstract: 본발명은개선된구조의멀티플라인그리드를갖는멀티플라인그리드어레이패키지를개시한다. 본발명은멀티플라인그리드는패키지몸체와같은크기로형성되며, 입출력노드와일대일대응하는위치에구멍이형성되며, 구멍에도전물질이충진및 도포되어단위리드를형성하여입출력노드에솔더링되는것을특징으로한다. 본발명에따르면, 일체형멀티플라인그리드를이용해입출력노드가배열된패키지몸체위에솔더링함으로써공정을단순화할수 있으며, 멀티플라인그리드의탑재정확도및 편평도를향상시켜열적특성및 전기적특성을향상시킬수 있는효과를얻을수 있다.